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| author | Pan Li <pan2.li@intel.com> | 2023-08-16 14:47:52 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-16 15:13:09 +0800 |
| commit | dc2529e8243859faf35c66d994756c40978f0ce5 (patch) | |
| tree | 4be7360c35a7ef710035555ee6b186f643e85ff7 /gcc/fold-const.cc | |
| parent | 567258f057913229084c21396b84c219f3fef05d (diff) | |
| download | gcc-dc2529e8243859faf35c66d994756c40978f0ce5.zip gcc-dc2529e8243859faf35c66d994756c40978f0ce5.tar.gz gcc-dc2529e8243859faf35c66d994756c40978f0ce5.tar.bz2 | |
RISC-V: Support RVV VFCVT.F.X.V and VFCVT.F.XU.V rounding mode intrinsic API
This patch would like to support the rounding mode API for the
VFCVT.F.X.V and VFCVT.F.XU.V as the below samples.
* __riscv_vfcvt_f_x_v_f32m1_rm
* __riscv_vfcvt_f_x_v_f32m1_rm_m
* __riscv_vfcvt_f_xu_v_f32m1_rm
* __riscv_vfcvt_f_xu_v_f32m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_f_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-f.c: New test.
Diffstat (limited to 'gcc/fold-const.cc')
0 files changed, 0 insertions, 0 deletions