rs6000: Generate mfvsrwz for all platforms and remove redundant zero extend

mfvsrwz has lower latency than xxextractuw or vextuw[lr]x.  So it should be
generated even with p9 vector enabled.  Also the instruction is already
zero extended.  A combine pattern is needed to eliminate redundant zero
extend instructions.

gcc/
	PR target/106769
	* config/rs6000/vsx.md (expand vsx_extract_<mode>): Set it only
	for V8HI and V16QI.
	(vsx_extract_v4si): New expand for V4SI extraction.
	(vsx_extract_v4si_w1): New insn pattern for V4SI extraction on
	word 1 from BE order.
	(*mfvsrwz): New insn pattern for mfvsrwz.
	(*vsx_extract_<mode>_di_p9): Assert that it won't be generated on
	word 1 from BE order.
	(*vsx_extract_si): Remove.
	(*vsx_extract_v4si_w023): New insn and split pattern on word 0, 2,
	3 from BE order.

gcc/testsuite/
	PR target/106769
	* gcc.target/powerpc/pr106769.h: New.
	* gcc.target/powerpc/pr106769-p8.c: New.
	* gcc.target/powerpc/pr106769-p9.c: New.

0 files changed, 0 insertions, 0 deletions