RISC-V: Add testcases for unsigned imm vec SAT_SUB form1

form1:
void __attribute__((noinline))             \
vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit)  \
{                                                   \
  unsigned i;                                       \
  for (i = 0; i < limit; i++)                       \
    out[i] = (T)IMM >= in[i] ? (T)IMM - in[i] : 0;  \
}

Passed the rv64gcv full regression test.

Signed-off-by: Li Xu <xuli1@eswincomputing.com>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: add data for vec sat_sub.
	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: add unsigned imm vec sat_sub form1.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c: New test.

0 files changed, 0 insertions, 0 deletions