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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-10-10 09:39:04 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-10-10 18:23:40 +0800 |
| commit | 4d230493f57dd11b8de9155b03088092f2ecea5c (patch) | |
| tree | 5b0185d3544aa777f9aca0ac29ed93004d0a0f79 /gcc/fold-const.cc | |
| parent | aaa5a5318adbefe87c1b781b8a3e5fc332e661ec (diff) | |
| download | gcc-4d230493f57dd11b8de9155b03088092f2ecea5c.zip gcc-4d230493f57dd11b8de9155b03088092f2ecea5c.tar.gz gcc-4d230493f57dd11b8de9155b03088092f2ecea5c.tar.bz2 | |
RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV
Here is the reference comparing dump IR between ARM SVE and RVV.
https://godbolt.org/z/zqess8Gss
We can see RVV has one more dump IR:
optimized: basic block part vectorized using 128 byte vectors
since RVV has 1024 bit vectors.
The codegen is reasonable good.
However, I saw GCN also has 1024 bit vector.
This patch may cause this case FAIL in GCN port ?
Hi, GCN folk, could you check this patch in GCN port for me ?
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-pr65935.c: Add vect1024 variant.
* lib/target-supports.exp: Ditto.
Diffstat (limited to 'gcc/fold-const.cc')
0 files changed, 0 insertions, 0 deletions