RISC-V: Bugfix for RVV float reduction in ZVE32/64

The rvv integer reduction has 3 different patterns for zve128+, zve64
and zve32. They take the same iterator with different attributions.
However, we need the generated function code_for_reduc (code, mode1, mode2).
The implementation of code_for_reduc may look like below.

code_for_reduc (code, mode1, mode2)
{
  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
    return CODE_FOR_pred_reduc_maxvnx1hfvnx16hf; // ZVE128+

  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
    return CODE_FOR_pred_reduc_maxvnx1hfvnx8hf;  // ZVE64

  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
    return CODE_FOR_pred_reduc_maxvnx1hfvnx4hf;  // ZVE32
}

Thus there will be a problem here. For example zve32, we will have
code_for_reduc (max, VNx1HF, VNx1HF) which will return the code of
the ZVE128+ instead of the ZVE32 logically.

This patch will merge the 3 patterns into pattern, and pass both the
input_vector and the ret_vector of code_for_reduc. For example, ZVE32
will be code_for_reduc (max, VNx1HF, VNx2HF), then the correct code of ZVE32
will be returned as expectation.

Please note both GCC 13 and 14 are impacted by this issue.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

	PR target/110277
	* config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
	ret_mode.
	* config/riscv/vector-iterators.md: Add VHF, VSF, VDF,
	VHF_LMUL1, VSF_LMUL1, VDF_LMUL1, and remove unused attr.
	* config/riscv/vector.md (@pred_reduc_<reduc><mode><vlmul1>): Removed.
	(@pred_reduc_<reduc><mode><vlmul1_zve64>): Ditto.
	(@pred_reduc_<reduc><mode><vlmul1_zve32>): Ditto.
	(@pred_reduc_plus<order><mode><vlmul1>): Ditto.
	(@pred_reduc_plus<order><mode><vlmul1_zve32>): Ditto.
	(@pred_reduc_plus<order><mode><vlmul1_zve64>): Ditto.
	(@pred_reduc_<reduc><VHF:mode><VHF_LMUL1:mode>): New pattern.
	(@pred_reduc_<reduc><VSF:mode><VSF_LMUL1:mode>): Ditto.
	(@pred_reduc_<reduc><VDF:mode><VDF_LMUL1:mode>): Ditto.
	(@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>): Ditto.
	(@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>): Ditto.
	(@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>): Ditto.

gcc/testsuite/ChangeLog:

	PR target/110277
	* gcc.target/riscv/rvv/base/pr110277-1.c: New test.
	* gcc.target/riscv/rvv/base/pr110277-1.h: New test.
	* gcc.target/riscv/rvv/base/pr110277-2.c: New test.
	* gcc.target/riscv/rvv/base/pr110277-2.h: New test.

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