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| author | liuhongt <hongtao.liu@intel.com> | 2022-06-06 13:39:19 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2022-06-07 17:32:21 +0800 |
| commit | cd22395457f063824c839fd1c0077d15d3dccd6d (patch) | |
| tree | 814dd38d0586a3902d8c2f37ba5d984b9563220d /gcc/expr.cc | |
| parent | c00e1e3aa5ae62a991d105d309061d12f6a8764f (diff) | |
| download | gcc-cd22395457f063824c839fd1c0077d15d3dccd6d.zip gcc-cd22395457f063824c839fd1c0077d15d3dccd6d.tar.gz gcc-cd22395457f063824c839fd1c0077d15d3dccd6d.tar.bz2 | |
Fix insn does not satisfy its constraints: sse2_lshrv1ti3
21114(define_insn_and_split "ssse3_palignrdi"
21115 [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
21116 (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
21117 (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yv")
21118 (match_operand:SI 3 "const_0_to_255_mul_8_operand")]
21119 UNSPEC_PALIGNR))]
21120 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
Alternative 2 requires Yw instead of Yv since it's splitted to vpsrldq
which requires AVX512VL & AVX512BW for evex version.
gcc/ChangeLog:
PR target/105854
* config/i386/sse.md (ssse3_palignrdi): Change alternative 2
from Yv to Yw.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr105854.c: New test.
Diffstat (limited to 'gcc/expr.cc')
0 files changed, 0 insertions, 0 deletions