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| author | Andrew Stubbs <ams@codesourcery.com> | 2023-11-14 16:07:37 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@codesourcery.com> | 2023-11-14 16:46:39 +0000 |
| commit | 948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3 (patch) | |
| tree | 793c26179d477114d316de1f196d638740ac790d /gcc/expr.cc | |
| parent | 1bdd665a025a74f4f1b641600a8c0bbca3355aa7 (diff) | |
| download | gcc-948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3.zip gcc-948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3.tar.gz gcc-948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3.tar.bz2 | |
Fix ICE generating uniform vector masks
Most targets have an "and" instructions for their vector mask size, but RISC-V
only has DImode "and". Fixed by allowing wider instruction modes.
gcc/ChangeLog:
PR target/112481
* expr.cc (store_constructor): Use OPTAB_WIDEN for mask adjustment.
Diffstat (limited to 'gcc/expr.cc')
| -rw-r--r-- | gcc/expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/expr.cc b/gcc/expr.cc index 3e2a678..556bcf7 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -7489,7 +7489,7 @@ store_constructor (tree exp, rtx target, int cleared, poly_int64 size, if (maybe_ne (GET_MODE_PRECISION (mode), nunits)) tmp = expand_binop (mode, and_optab, tmp, GEN_INT ((1 << nunits) - 1), target, - true, OPTAB_DIRECT); + true, OPTAB_WIDEN); if (tmp != target) emit_move_insn (target, tmp); break; |