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| author | Pan Li <pan2.li@intel.com> | 2023-06-04 14:15:15 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-06-04 21:39:22 +0800 |
| commit | 5c9cffa3a4aeeac1e462dbc8a35a5c4986f3381e (patch) | |
| tree | e32d07ce4ea1802429c88317fdce3ef2de4b6b7f /gcc/expr.cc | |
| parent | 1330977166aa8b3035b6314f5d3bac362f77be6b (diff) | |
| download | gcc-5c9cffa3a4aeeac1e462dbc8a35a5c4986f3381e.zip gcc-5c9cffa3a4aeeac1e462dbc8a35a5c4986f3381e.tar.gz gcc-5c9cffa3a4aeeac1e462dbc8a35a5c4986f3381e.tar.bz2 | |
RISC-V: Support RVV FP16 ZVFHMIN intrinsic API
This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
SEW=16 for below instructions
vfwcvt.f.f.v
vfncvt.f.f.w
Then users can leverage the instrinsic APIs to perform the conversion
between RVV vector single float point and half float point.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-types.def
(vfloat32mf2_t): Add vfloat32mf2_t type to vfncvt.f.f.w operations.
(vfloat32m1_t): Likewise.
(vfloat32m2_t): Likewise.
(vfloat32m4_t): Likewise.
(vfloat32m8_t): Likewise.
* config/riscv/riscv-vector-builtins.def: Fix typo in comments.
* config/riscv/vector-iterators.md: Add single to half machine
mode conversion.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: New test.
Diffstat (limited to 'gcc/expr.cc')
0 files changed, 0 insertions, 0 deletions