Fix riscv_expand_conditional_move.

Two issues have been observed in current riscv_expand_conditional_move
implementation.
1. Before introduction of TARGET_XTHEADCONDMOV, op0 of comparision expression
is used for mode comparision with word_mode, but after TARGET_XTHEADCONDMOV
megered with TARGET_SFB_ALU, dest of if-then-else is used for mode comparision with
word_mode, and from md file mode of dest is DI or SI which can be different with
word_mode in RV64.

2. TARGET_XTHEADCONDMOV cannot be generated when the mode of the comparison is E_VOID.

This patch solves the issues above.

Provide an example from the newly added test case.

Testcase:
int ConNmv_reg_reg_reg(int x, int y, int z, int n){
  if (x != y) return z;
  return n;
}

Cflags:
-O2 -march=rv64gc_xtheadcondmov -mabi=lp64d

before patch:
ConNmv_reg_reg_reg:
	bne	a0,a1,.L23
	mv	a2,a3
.L23:
	mv	a0,a2
	ret

after patch:
ConNmv_reg_reg_reg:
	sub	a1,a0,a1
	th.mveqz	a2,zero,a1
	th.mvnez	a3,zero,a1
	or	a0,a2,a3
	ret

Co-Authored by: Fei Gao <gaofei@eswincomputing.com>
Signed-off-by: Die Li <lidie@eswincomputing.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_conditional_move): Fix mode
	checking.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadcondmov-indirect-rv32.c: New test.
	* gcc.target/riscv/xtheadcondmov-indirect-rv64.c: New test.

0 files changed, 0 insertions, 0 deletions