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authorPan Li <pan2.li@intel.com>2023-06-07 09:25:33 +0800
committerPan Li <pan2.li@intel.com>2023-06-07 10:28:44 +0800
commit42eb371286fa4f1f8419ff9e8059576e574c7a2c (patch)
treecb2ef34fc1aaaef86ad15ff65189ab620199b238 /gcc/expr.cc
parent2ae5384d457b9c67586de012816dfc71a6943164 (diff)
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RISC-V: Fix ICE when include riscv_vector.h with rv64gcv
This patch would like to fix the incorrect requirement of the vector builtin types for the ZVFH/ZVFHMIN extension. The incorrect requirement will result in the ops mismatch with iterators, and then ICE will be triggered if ZVFH/ZVFHMIN is not given. Sorry for inconviensient. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * config/riscv/riscv-vector-builtins-types.def (vfloat32mf2_t): Take RVV_REQUIRE_ELEN_FP_16 as requirement. (vfloat32m1_t): Ditto. (vfloat32m2_t): Ditto. (vfloat32m4_t): Ditto. (vfloat32m8_t): Ditto. (vint16mf4_t): Ditto. (vint16mf2_t): Ditto. (vint16m1_t): Ditto. (vint16m2_t): Ditto. (vint16m4_t): Ditto. (vint16m8_t): Ditto. (vuint16mf4_t): Ditto. (vuint16mf2_t): Ditto. (vuint16m1_t): Ditto. (vuint16m2_t): Ditto. (vuint16m4_t): Ditto. (vuint16m8_t): Ditto. (vint32mf2_t): Ditto. (vint32m1_t): Ditto. (vint32m2_t): Ditto. (vint32m4_t): Ditto. (vint32m8_t): Ditto. (vuint32mf2_t): Ditto. (vuint32m1_t): Ditto. (vuint32m2_t): Ditto. (vuint32m4_t): Ditto. (vuint32m8_t): Ditto.
Diffstat (limited to 'gcc/expr.cc')
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