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| author | Joern Rennecke <joern.rennecke@embecosm.com> | 2023-05-19 16:18:42 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-05-19 16:19:51 -0600 |
| commit | 259b4b7d349dd3fd560144bd4617f526458b45dc (patch) | |
| tree | af02364e25755ac8b817151407085277c3dac23e /gcc/expr.cc | |
| parent | ae2345285c28549145af203ef8161ff96e2ad877 (diff) | |
| download | gcc-259b4b7d349dd3fd560144bd4617f526458b45dc.zip gcc-259b4b7d349dd3fd560144bd4617f526458b45dc.tar.gz gcc-259b4b7d349dd3fd560144bd4617f526458b45dc.tar.bz2 | |
RISC-V: Remove masking third operand of rotate instructions
Sorry, I forgot the ChangeLog entry for my patch and missed the [v2]
part of the subject.
2023-05-18 Joern Rennecke <joern.rennecke@embecosm.com>
gcc/ChangeLog:
* config/riscv/constraints.md (DsS, DsD): Restore agreement
with shiftm1 mode attribute.
Diffstat (limited to 'gcc/expr.cc')
0 files changed, 0 insertions, 0 deletions