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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-05-03 12:02:54 +0100 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-12-06 21:18:29 +0000 |
| commit | 16a05fac33ddde7a50da9cb937a9b83ea7c111f6 (patch) | |
| tree | a108fed5c523ac1eebc0f9370b0795a2451e015f /gcc/expr.cc | |
| parent | 1bd15d87031e8bf8fe9585fbc166b315303f676c (diff) | |
| download | gcc-16a05fac33ddde7a50da9cb937a9b83ea7c111f6.zip gcc-16a05fac33ddde7a50da9cb937a9b83ea7c111f6.tar.gz gcc-16a05fac33ddde7a50da9cb937a9b83ea7c111f6.tar.bz2 | |
aarch64: Add march flags for +the and +d128 arch extensions
Given the introduction of optional 128-bit page table descriptor and
translation hardening extension support with the Arm9.4-a
architecture, this introduces the relevant flags to enable the reading
and writing of 128-bit system registers.
The `+d128' -march modifier enables the use of the following ACLE
builtin functions:
* __uint128_t __arm_rsr128(const char *special_register);
* void __arm_wsr128(const char *special_register, __uint128_t value);
and defines the __ARM_FEATURE_SYSREG128 macro to 1.
Finally, the `rcwmask_el1' and `rcwsmask_el1' 128-bit system register
implementations are also reliant on the enablement of the `+the' flag,
which is thus also implemented in this patch.
gcc/ChangeLog:
* config/aarch64/aarch64-c.cc (__ARM_FEATURE_SYSREG128): New.
* config/aarch64/aarch64-arches.def (armv8.9-a): New.
(armv9.4-a): Likewise.
* config/aarch64/aarch64-option-extensions.def (d128): Likewise.
(the): Likewise.
* config/aarch64/aarch64.h (AARCH64_ISA_V9_4A): Likewise.
(AARCH64_ISA_V8_9A): Likewise.
(TARGET_ARMV9_4): Likewise.
(AARCH64_ISA_D128): Likewise.
(AARCH64_ISA_THE): Likewise.
(TARGET_D128): Likewise.
* doc/invoke.texi (AArch64 Options): Document new -march flags
and extensions.
Diffstat (limited to 'gcc/expr.cc')
0 files changed, 0 insertions, 0 deletions