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| author | Pan Li <pan2.li@intel.com> | 2025-01-27 11:01:08 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2025-01-29 17:36:29 +0800 |
| commit | 7ab7829aef6b02d4022650566b2806af986be0cb (patch) | |
| tree | e231abec43835857f534a3376e157dc9987b00b5 /gcc/expr.cc | |
| parent | 7b02b8f65ef60be77f3f93945e2a6b463edaa0aa (diff) | |
| download | gcc-7ab7829aef6b02d4022650566b2806af986be0cb.zip gcc-7ab7829aef6b02d4022650566b2806af986be0cb.tar.gz gcc-7ab7829aef6b02d4022650566b2806af986be0cb.tar.bz2 | |
RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC]
This patch would like to refactor the helper function of the SAT_*
scalar. The helper function will convert the define_pattern ops
to the xmode reg for the underlying code-gen. This patch add
new parameter for ZERO_EXTEND or SIGN_EXTEND if the input is const_int
or the mode is non-Xmode.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Rename from ...
(riscv_extend_to_xmode_reg): Rename to and add rtx_code for
zero/sign extend if non-Xmode.
(riscv_expand_usadd): Leverage the renamed function with ZERO_EXTEND.
(riscv_expand_ussub): Ditto.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/expr.cc')
0 files changed, 0 insertions, 0 deletions