RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.

This commit adds intrinsics support for Xsfvqmaccqoq/dod.

Co-Authored by: Jiawei Chen <jiawei@iscas.ac.cn>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yixuan Chen <chenyixuan@iscas.ac.cn>

gcc/ChangeLog:

	* config.gcc: Add new SiFive *.o files.
	* config/riscv/generic-vector-ooo.md: New reservation.
	* config/riscv/genrvv-type-indexer.cc (main): New type.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct sf_vqmacc_def): New function.
	(SHAPE): Ditto.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_QMACC_OPS): New macros type.
	(vint32m1_t): Ditto.
	(vint32m2_t): Ditto.
	(vint32m4_t): Ditto.
	(vint32m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_QMACC_OPS): New builtins def.
	(DEF_RVV_TYPE_INDEX): Ditto.
	(DEF_RVV_FUNCTION): Ditto.
	* config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE_INDEX): New types def.
	(4x8x4): New op type.
	(2x8x2): Ditto.
	(quad_emul_vector): New base type.
	(quad_emul_signed_vector): Ditto.
	(quad_emul_unsigned_vector): Ditto.
	(quad_fixed_vector): Ditto.
	(quad_fixed_signed_vector): Ditto.
	(quad_fixed_unsigned_vector): Ditto.
	(quad_lmul1_vector): Ditto.
	(quad_lmul1_signed_vector): Ditto.
	(quad_lmul1_unsigned_vector): Ditto.
	* config/riscv/riscv-vector-builtins.h (enum required_ext): New extensions.
	(required_ext_to_isa_name): Ditto.
	(required_extensions_specified): Ditto.
	(struct function_group_info): Ditto.
	* config/riscv/riscv.md: New attr.
	* config/riscv/t-riscv: Add include for SiFive files.
	* config/riscv/vector-iterators.md: New iterator.
	* config/riscv/vector.md: New include for SiFive file.
	* config/riscv/sifive-vector-builtins-bases.cc: New file.
	* config/riscv/sifive-vector-builtins-bases.h: New file.
	* config/riscv/sifive-vector-builtins-functions.def: New file.
	* config/riscv/sifive-vector.md: New file.

0 files changed, 0 insertions, 0 deletions