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| author | Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com> | 2024-01-12 16:44:20 +0800 |
|---|---|---|
| committer | Christoph Müllner <christoph.muellner@vrull.eu> | 2024-01-18 15:40:07 +0100 |
| commit | 9e1b554cc75e25fe96baf9b8d7963b932cb2c36d (patch) | |
| tree | 9ad7b736df0397e1c2b4e1bbe91688a58ac74deb /gcc/expr.cc | |
| parent | cdf4729f0889501c622cc1ad2df9377f2819cc07 (diff) | |
| download | gcc-9e1b554cc75e25fe96baf9b8d7963b932cb2c36d.zip gcc-9e1b554cc75e25fe96baf9b8d7963b932cb2c36d.tar.gz gcc-9e1b554cc75e25fe96baf9b8d7963b932cb2c36d.tar.bz2 | |
RISC-V: Rewrite some instructions using ASM targethook
There are some xtheadvector instructions that differ from RVV1.0
apart from simply adding "th." prefix. For example, RVV1.0
load/store instructions will have SEW while xtheadvector not;
RVV1.0 will have "o" for indexed-ordered store instructions while
xtheadvecotr not; xtheadvector and RVV1.0 have different
vnsrl/vnsra/vfncvt suffix (vv/vx/vi vs wv/wx/wi).
To address this issue without duplicating patterns, we use ASM
targethook to rewrite the whole string of the instructions. We
identify different instructions from the corresponding attribute.
gcc/ChangeLog:
* config/riscv/thead.cc
(th_asm_output_opcode): Rewrite some instructions.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gcc/expr.cc')
0 files changed, 0 insertions, 0 deletions