aarch64: rcpc3: Add relevant iterators to handle Neon intrinsics

The LDAP1 and STL1 Neon ACLE intrinsics, operating on 64-bit data
values, operate on single-lane (Vt.1D) or twin-lane (Vt.2D) SIMD
register configurations, either in the DI or DF modes.  This leads to
the need for a mode iterator accounting for the V1DI, V1DF, V2DI and
V2DF modes.

This patch therefore introduces the new V12DIF mode iterator with
which to generate functions operating on signed 64-bit integer and
float values and V12DIUP for generating the unsigned and
polynomial-type counterparts.  Along with this, we modify the
associated mode attributes accordingly in order to allow for the
implementation of the relevant backend patterns for the intrinsics.

gcc/ChangeLog:

	* config/aarch64/iterators.md (V12DIF): New.
	(V12DUP): Likewise.
	(VEL): Add support for all V12DIF-associated modes.
	(Vetype): Add support for V1DI and V1DF.
	(Vel): Likewise.

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