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| author | Pan Li <pan2.li@intel.com> | 2024-09-02 15:54:43 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-09-04 08:21:11 +0800 |
| commit | 9ea9d05908432fc5f3632f3e397e3709f95ef636 (patch) | |
| tree | 57e6002235af6c69440bf4da3f84e944727c4786 /gcc/expr.cc | |
| parent | d8bc31d973d2ab3fabb5e85e7c4354ffb2283512 (diff) | |
| download | gcc-9ea9d05908432fc5f3632f3e397e3709f95ef636.zip gcc-9ea9d05908432fc5f3632f3e397e3709f95ef636.tar.gz gcc-9ea9d05908432fc5f3632f3e397e3709f95ef636.tar.bz2 | |
RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD
This patch would like to allow the IMM operand of the unsigned
scalar .SAT_ADD. Like the operand 0, the operand 1 of .SAT_ADD
will be zero extended to Xmode before underlying code generation.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_usadd): Zero extend
the second operand of usadd as the first operand does.
* config/riscv/riscv.md (usadd<m>3): Allow imm operand for
scalar usadd pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_u_add-11.c: Make asm check robust.
* gcc.target/riscv/sat_u_add-15.c: Ditto.
* gcc.target/riscv/sat_u_add-19.c: Ditto.
* gcc.target/riscv/sat_u_add-23.c: Ditto.
* gcc.target/riscv/sat_u_add-3.c: Ditto.
* gcc.target/riscv/sat_u_add-7.c: Ditto.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/expr.cc')
0 files changed, 0 insertions, 0 deletions