diff options
| author | Richard Guenther <rguenther@suse.de> | 2012-01-24 09:17:01 +0000 |
|---|---|---|
| committer | Richard Biener <rguenth@gcc.gnu.org> | 2012-01-24 09:17:01 +0000 |
| commit | a9d3ac1e891f37fe405d8aaa4653d27ed818871c (patch) | |
| tree | 438895843443c1acc2e945d7b7c332cad7bdd785 /gcc/expr.c | |
| parent | 93bcc8c9ff361dbf3f42c9dcced458acfb5e994d (diff) | |
| download | gcc-a9d3ac1e891f37fe405d8aaa4653d27ed818871c.zip gcc-a9d3ac1e891f37fe405d8aaa4653d27ed818871c.tar.gz gcc-a9d3ac1e891f37fe405d8aaa4653d27ed818871c.tar.bz2 | |
[multiple changes]
2012-01-24 Richard Guenther <rguenther@suse.de>
Forward-port to trunk
2010-09-21 Jakub Jelinek <jakub@redhat.com>
PR middle-end/45678
* expr.c (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: If
op0 isn't sufficiently aligned and there is movmisalignM
insn for mode, use it to load op0 into a temporary register.
From-SVN: r183470
Diffstat (limited to 'gcc/expr.c')
| -rw-r--r-- | gcc/expr.c | 22 |
1 files changed, 22 insertions, 0 deletions
@@ -10044,10 +10044,32 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode, results. */ if (MEM_P (op0)) { + enum insn_code icode; + op0 = copy_rtx (op0); if (TYPE_ALIGN_OK (type)) set_mem_align (op0, MAX (MEM_ALIGN (op0), TYPE_ALIGN (type))); + else if (mode != BLKmode + && MEM_ALIGN (op0) < GET_MODE_ALIGNMENT (mode) + /* If the target does have special handling for unaligned + loads of mode then use them. */ + && ((icode = optab_handler (movmisalign_optab, mode)) + != CODE_FOR_nothing)) + { + rtx reg, insn; + + op0 = adjust_address (op0, mode, 0); + /* We've already validated the memory, and we're creating a + new pseudo destination. The predicates really can't + fail. */ + reg = gen_reg_rtx (mode); + + /* Nor can the insn generator. */ + insn = GEN_FCN (icode) (reg, op0); + emit_insn (insn); + return reg; + } else if (STRICT_ALIGNMENT && mode != BLKmode && MEM_ALIGN (op0) < GET_MODE_ALIGNMENT (mode)) |