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authorEric Botcazou <ebotcazou@adacore.com>2014-02-19 14:45:16 +0000
committerEric Botcazou <ebotcazou@gcc.gnu.org>2014-02-19 14:45:16 +0000
commit322913f8769f6c7cac6a992debb430757e0e0c05 (patch)
treeac0e212d9e729fb65c18549463678f0d9037031a /gcc/expr.c
parentffdeb7023fb9bff52a925e785715b9d24a2484dd (diff)
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expr.c (expand_expr_real_1): For a bit-field destination type...
* expr.c (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: For a bit-field destination type, extract only the valid bits if the source type is not integral and has a different mode. From-SVN: r207902
Diffstat (limited to 'gcc/expr.c')
-rw-r--r--gcc/expr.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/gcc/expr.c b/gcc/expr.c
index 29ce694..be62c53 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -10436,6 +10436,11 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
else if (INTEGRAL_TYPE_P (type) && INTEGRAL_TYPE_P (TREE_TYPE (treeop0)))
op0 = convert_modes (mode, GET_MODE (op0), op0,
TYPE_UNSIGNED (TREE_TYPE (treeop0)));
+ /* If the output type is a bit-field type, do an extraction. */
+ else if (reduce_bit_field)
+ return extract_bit_field (op0, TYPE_PRECISION (type), 0,
+ TYPE_UNSIGNED (type), NULL_RTX,
+ mode, mode);
/* As a last resort, spill op0 to memory, and reload it in a
different mode. */
else if (!MEM_P (op0))
@@ -10458,10 +10463,10 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
op0 = target;
}
- /* At this point, OP0 is in the correct mode. If the output type is
- such that the operand is known to be aligned, indicate that it is.
- Otherwise, we need only be concerned about alignment for non-BLKmode
- results. */
+ /* If OP0 is (now) a MEM, we need to deal with alignment issues. If the
+ output type is such that the operand is known to be aligned, indicate
+ that it is. Otherwise, we need only be concerned about alignment for
+ non-BLKmode results. */
if (MEM_P (op0))
{
enum insn_code icode;