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authorliuhongt <hongtao.liu@intel.com>2020-05-26 11:14:31 +0800
committerliuhongt <hongtao.liu@intel.com>2020-05-26 11:41:15 +0800
commit9d0dc47de6ed9609fe7445ea0941a6a822c80f88 (patch)
tree42c72bdd1af98da7af0e6f454ecd133ebde4eb41 /gcc/emit-rtl.c
parent0b0d9a77d0a00b79b5f19e7428d8004a68f00180 (diff)
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Fix non-comforming expander for floatv2div2sf2,floatunsv2div2sf2,fix_truncv2sfv2di,fixuns_truncv2sfv2di.
2020-05-26 Hongtao Liu <hongtao.liu@intel.com> Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/95211 PR target/95256 * config/i386/sse.md (<floatunssuffix>v2div2sf2): New expander. (fix<fixunssuffix>_truncv2sfv2di2): Ditto. (avx512dq_float<floatunssuffix>v2div2sf2): Renaming from float<floatunssuffix>v2div2sf2. (avx512dq_fix<fixunssuffix>_truncv2sfv2di2<mask_name>): Renaming from fix<fixunssuffix>_truncv2sfv2di2<mask_name>. (vec_pack<floatprefix>_float_<mode>): Adjust icode name. (vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Ditto. (vec_unpack_<fixprefix>fix_trunc_hi_<mode>): Ditto. * config/i386/i386-builtin.def: Ditto. * emit-rtl.c (validate_subreg): Allow use of *paradoxical* vector subregs when both omode and imode are vector mode and have the same inner mode. gcc/testsuite/ChangeLog * gcc.target/i386/pr95211.c: New test.
Diffstat (limited to 'gcc/emit-rtl.c')
-rw-r--r--gcc/emit-rtl.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
index c496280..2b790636 100644
--- a/gcc/emit-rtl.c
+++ b/gcc/emit-rtl.c
@@ -939,11 +939,13 @@ validate_subreg (machine_mode omode, machine_mode imode,
&& GET_MODE_INNER (imode) == omode)
;
/* ??? x86 sse code makes heavy use of *paradoxical* vector subregs,
- i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to
- represent this. It's questionable if this ought to be represented at
- all -- why can't this all be hidden in post-reload splitters that make
- arbitrarily mode changes to the registers themselves. */
- else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode)
+ i.e. (subreg:V4SF (reg:SF) 0) or (subreg:V4SF (reg:V2SF) 0). This
+ surely isn't the cleanest way to represent this. It's questionable
+ if this ought to be represented at all -- why can't this all be hidden
+ in post-reload splitters that make arbitrarily mode changes to the
+ registers themselves. */
+ else if (VECTOR_MODE_P (omode)
+ && GET_MODE_INNER (omode) == GET_MODE_INNER (imode))
;
/* Subregs involving floating point modes are not allowed to
change size. Therefore (subreg:DI (reg:DF) 0) is fine, but