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authorJim Wilson <jimw@sifive.com>2020-11-13 18:12:24 -0800
committerJim Wilson <jimw@sifive.com>2020-11-13 18:12:35 -0800
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parenta4dd85e01599890286d9af5b106a1ab20e51169e (diff)
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Asan changes for RISC-V.
We have only riscv64 asan support, there is no riscv32 support as yet. So I need to be able to conditionally enable asan support for the riscv target. I implemented this by returning zero from the asan_shadow_offset function. This requires a change to toplev.c and docs in target.def. gcc/ * config/riscv/riscv.c (riscv_asan_shadow_offset): New. (TARGET_ASAN_SHADOW_OFFSET): New. * doc/tm.texi: Regenerated. * target.def (asan_shadow_offset); Mention that it can return zero. * toplev.c (process_options): Check for and handle zero return from targetm.asan_shadow_offset call. Co-Authored-By: cooper.joshua <cooper.joshua@linux.alibaba.com>
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