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author | Artemiy Volkov <Artemiy.Volkov@synopsys.com> | 2024-06-23 14:54:00 -0600 |
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committer | Jeff Law <jlaw@ventanamicro.com> | 2024-06-23 14:54:56 -0600 |
commit | eb647daa87b466d0a71246fad302cd81bfce9be5 (patch) | |
tree | 7b35d1941e1744e83c2a5f098341704e8b42714f /gcc/dwarf2codeview.h | |
parent | fd536b8412d4dae42aa04739c06f99a915be6261 (diff) | |
download | gcc-eb647daa87b466d0a71246fad302cd81bfce9be5.zip gcc-eb647daa87b466d0a71246fad302cd81bfce9be5.tar.gz gcc-eb647daa87b466d0a71246fad302cd81bfce9be5.tar.bz2 |
[PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move()
Presently, the code fragment:
int x[5];
void
d(int a, int b, int c) {
for (int i = 0; i < 5; i++)
x[i] = (a != b) ? c : a;
}
causes an ICE when compiled with -O2 -march=rv32i_zicond:
test.c: In function 'd':
test.c: error: unrecognizable insn:
11 | }
| ^
(insn 8 5 9 2 (set (reg:SI 139 [ iftmp.0_2 ])
(if_then_else:SI (ne:SI (reg/v:SI 136 [ a ])
(reg/v:SI 137 [ b ]))
(reg/v:SI 136 [ a ])
(reg/v:SI 138 [ c ]))) -1
(nil))
during RTL pass: vregs
This happens because, as part of one of the optimizations in
riscv_expand_conditional_move(), an if_then_else is generated with both
comparands being register operands, resulting in an unmatchable insn since
Zicond patterns require constant 0 as the second comparand. Fix this by adding
a extra check before performing this optimization.
The code snippet mentioned above is also included in this patch as a new Zicond
testcase.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_conditional_move): Add a
CONST0_RTX check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond-ice-5.c: New test.
Diffstat (limited to 'gcc/dwarf2codeview.h')
0 files changed, 0 insertions, 0 deletions