diff options
| author | Oleg Endo <olegendo@gcc.gnu.org> | 2012-07-26 00:19:58 +0000 |
|---|---|---|
| committer | Oleg Endo <olegendo@gcc.gnu.org> | 2012-07-26 00:19:58 +0000 |
| commit | f34ee0b290fe3e188bcda2985c071b031381a67b (patch) | |
| tree | bad46d3b39d836f1907345d5b96a602cd0993faa /gcc/doc | |
| parent | 3b29b58c1b1cf300383506e269d6596050105b53 (diff) | |
| download | gcc-f34ee0b290fe3e188bcda2985c071b031381a67b.zip gcc-f34ee0b290fe3e188bcda2985c071b031381a67b.tar.gz gcc-f34ee0b290fe3e188bcda2985c071b031381a67b.tar.bz2 | |
re PR target/51244 ([SH] Inefficient conditional branch and code around T bit)
PR target/51244
* config/sh/sh.opt (mzdcbranch): New option.
* doc/invoke.texi: Document it.
* config/sh/sh.md (negsi_cond): Use TARGET_ZDCBRANCH as condition
instead of TARGET_HARD_SH4.
* config/sh/sh.c (sh_option_override): Set TARGET_ZDCBRANCH as default
for TARGET_HARD_SH4.
From-SVN: r189877
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cba685d..429fdc8 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -889,8 +889,9 @@ See RS/6000 and PowerPC Options. -mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol -maccumulate-outgoing-args -minvalid-symbols -msoft-atomic -mhard-atomic @gol --mbranch-cost=@var{num} -mcbranchdi -mcmpeqdi -mfused-madd -mno-fused-madd @gol --mfsca -mno-fsca -mfsrra -mno-fsrra -mpretend-cmove -menable-tas} +-mbranch-cost=@var{num} -mzdcbranch -mno-zdcbranch -mcbranchdi -mcmpeqdi @gol +-mfused-madd -mno-fused-madd -mfsca -mno-fsca -mfsrra -mno-fsrra @gol +-mpretend-cmove -menable-tas} @emph{Solaris 2 Options} @gccoptlist{-mimpure-text -mno-impure-text @gol @@ -18366,6 +18367,16 @@ make the compiler try to generate more branch-free code if possible. If not specified the value is selected depending on the processor type that is being compiled for. +@item -mzdcbranch +@itemx -mno-zdcbranch +@opindex mzdcbranch +@opindex mno-zdcbranch +Assume (do not assume) that zero displacement conditional branch instructions +@code{bt} and @code{bf} are fast. If @option{-mzdcbranch} is specified, the +compiler will try to prefer zero displacement branch code sequences. This is +enabled by default when generating code for SH4 and SH4A. It can be explicitly +disabled by specifying @option{-mno-zdcbranch}. + @item -mcbranchdi @opindex mcbranchdi Enable the @code{cbranchdi4} instruction pattern. |