tm.texi (TARGET_IRA_COVER_CLASSES): Modify description.

2008-12-09  Vladimir Makarov  <vmakarov@redhat.com>

	* doc/tm.texi (TARGET_IRA_COVER_CLASSES): Modify description.

	* doc/invoke.texi (-fira-region): Describe new option.
	(-fira-algorithm): Change the values.

	* ira-conflicts.c (build_conflict_bit_table,
	build_allocno_conflicts): Use ira_reg_classes_intersect_p.
	(ira_build_conflicts): Use flag flag_ira_region instead of
	flag_ira_algorithm.  Prohibit usage of callee-saved likely spilled
	base registers for allocnos crossing calls.

	* flags.h (enum ira_algorithm): Redefine.
	(enum ira_region): New.
	(flag_ira_region): New.

	* cfgloopanal.c (estimate_reg_pressure_cost): Use flag_ira_region
	instead of flag_ira_algorithm.

	* toplev.c (flag_ira_algorithm): Change the initial value.
	(flag_ira_region): New.

	* ira-int.h (ira_reg_classes_intersect_p,
	ira_reg_class_super_classes): New.

	* ira-color.c (update_copy_costs): Use
	ira_reg_classes_intersect_p.  Use right class to find hard reg
	index.
	(update_conflict_hard_regno_costs): Ditto.  Add a new parameter.
	(assign_hard_reg): Ditto.  Pass additional argument to
	update_conflict_hard_regno_costs.  Do not uncoalesce for priority
	coloring.
	(allocno_priorities, setup_allocno_priorities,
	allocno_priority_compare_func): Move before color_allocnos.
	(color_allocnos): Add priority coloring.  Use flag flag_ira_region
	instead of flag_ira_algorithm.
	(move_spill_restore): Check classes of the same reg allocno from
	different regions.
	(update_curr_costs): Use ira_reg_classes_intersect_p.
	(ira_reassign_conflict_allocnos): Ditto.

	* opts.c (decode_options): Always set up flag_ira.  Set up
	flag_ira_algorithm.  Warn CB can not be used for architecture.
	(common_handle_option): Modify code for -fira-algorithm.  Add code
	to process -fira-region.

	* ira-lives.c (update_allocno_pressure_excess_length): Process
	superclasses too.
	(set_allocno_live, clear_allocno_live, mark_reg_live,
	mark_reg_dead, process_bb_node_lives): Ditto.

	* ira-emit.c (ira_emit): Fix insn codes.
	
	* ira-build.c (propagate_allocno_info): Use flag flag_ira_region
	instead of flag_ira_algorithm.
	(allocno_range_compare_func): Ignore classes for priority
	coloring.
	(setup_min_max_conflict_allocno_ids): Ditto.
	(ira_flattening): Use ira_reg_classes_intersect_p.

	* genpreds.c (write_enum_constraint_num): Output
	CONSTRAINT__LIMIT.
	
	* common.opt (fira-algorithm): Modify.
	(fira-region): New.

	* ira.c (setup_class_hard_regs): Initialize.
	(setup_cover_and_important_classes): Modify code setting class
	related info for priority coloring.
	(setup_class_translate): Ditto.
	(ira_reg_classes_intersect_p, ira_reg_class_super_classes): New.
	(setup_reg_class_intersect_union): Rename to
	setup_reg_class_relations.  Add code for setting up new variables.
	(find_reg_class_closure): Do not check targetm.ira_cover_classes.
	(ira): Use flag flag_ira_region instead of flag_ira_algorithm.

	* ira-costs.c (common_classes): New.
	(print_costs): Use flag flag_ira_region instead of
	flag_ira_algorithm.
	(find_allocno_class_costs): Ditto.  Use common_classes.  Translate
	alt_class.
	(ira_costs): Allocate/deallocate common_classes.
	
	* config/m32c/m32.h (REG_ALLOC_ORDER): Add reg 19.
	(REG_CLASS_CONTENTS, reg_class, REG_CLASS_NAMES): New entries for
	R02A_REGS.

	* reload1.c (choose_reload_regs): Use MODE_INT for partial ints in
	smallest_mode_for_size.

From-SVN: r142610

2 files changed, 22 insertions, 13 deletions

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 7e6da15..66d28c7 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -338,7 +338,7 @@ Objective-C and Objective-C++ Dialects}.
 -finline-small-functions -fipa-cp -fipa-cp-clone -fipa-matrix-reorg -fipa-pta @gol 
 -fipa-pure-const -fipa-reference -fipa-struct-reorg @gol
 -fipa-type-escape -fira -fira-algorithm=@var{algorithm} @gol
--fira-coalesce -fno-ira-share-save-slots @gol
+-fira-region=@var{region} -fira-coalesce -fno-ira-share-save-slots @gol
 -fno-ira-share-spill-slots -fira-verbose=@var{n} @gol
 -fivopts -fkeep-inline-functions -fkeep-static-consts @gol
 -floop-block -floop-interchange -floop-strip-mine @gol
@@ -5728,17 +5728,25 @@ allocation.  It is a default if @acronym{IRA} has been ported for the
 target.
 
 @item -fira-algorithm=@var{algorithm}
-Use specified algorithm for the integrated register allocator.  The
-@var{algorithm} argument should be one of @code{regional}, @code{CB},
-or @code{mixed}.  The second algorithm specifies Chaitin-Briggs
-coloring, the first one specifies regional coloring based on
-Chaitin-Briggs coloring, and the third one which is the default
-specifies a mix of Chaitin-Briggs and regional algorithms where loops
-with small register pressure are ignored.  The first algorithm can
-give best result for machines with small size and irregular register
-set, the second one is faster and generates decent code and the
-smallest size code, and the mixed algorithm usually give the best
-results in most cases and for most architectures.
+Use specified coloring algorithm for the integrated register
+allocator.  The @var{algorithm} argument should be @code{priority} or
+@code{CB}.  The first algorithm specifies Chow's priority coloring,
+the second one specifies Chaitin-Briggs coloring.  The second
+algorithm can be unimplemented for some architectures.  If it is
+implemented, it is the default because Chaitin-Briggs coloring as a
+rule generates a better code.
+
+@item -fira-region=@var{region}
+Use specified regions for the integrated register allocator.  The
+@var{region} argument should be one of @code{all}, @code{mixed}, or
+@code{one}.  The first value means using all loops as register
+allocation regions, the second value which is the default means using
+all loops except for loops with small register pressure as the
+regions, and third one means using all function as a single region.
+The first value can give best result for machines with small size and
+irregular register set, the third one results in faster and generates
+decent code and the smallest size code, and the default value usually
+give the best results in most cases and for most architectures.
 
 @item -fira-coalesce
 @opindex fira-coalesce
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 7dfb46b..5a76a6e 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -2841,7 +2841,8 @@ options have been processed. It is then re-examined by every call to
 The default implementation returns @code{IRA_COVER_CLASSES}, if defined,
 otherwise there is no default implementation.  You must define either this
 macro or @code{IRA_COVER_CLASSES} in order to use the integrated register
-allocator for the target.
+allocator with Chaitin-Briggs coloring. If the macro is not defined,
+the only available coloring algorithm is Chow's priority coloring.
 @end deftypefn
 
 @defmac IRA_COVER_CLASSES