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author | Peter Bergner <bergner@vnet.ibm.com> | 2009-10-10 13:43:31 -0500 |
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committer | Peter Bergner <bergner@gcc.gnu.org> | 2009-10-10 13:43:31 -0500 |
commit | 47f67e51560a5cb55fa2720bcb56d0d29a53ca85 (patch) | |
tree | afc2dd124fe7531142ce2fd55c5ebfac23f5497d /gcc/doc | |
parent | b6ebf72767b63ccd3754b5e7ff319e8f587005dd (diff) | |
download | gcc-47f67e51560a5cb55fa2720bcb56d0d29a53ca85.zip gcc-47f67e51560a5cb55fa2720bcb56d0d29a53ca85.tar.gz gcc-47f67e51560a5cb55fa2720bcb56d0d29a53ca85.tar.bz2 |
configure.ac: Add test for dci instruction.
* configure.ac: Add test for dci instruction.
* configure: Regenerate.
* config.in: Likewise.
* config.gcc: Handle --with-cpu=476 and --with-cpu=476fp.
* doc/invoke.texi: Add cpu_type 476 and 476fp.
(-mmulhw): Add 476 to description.
(-mdlmzb): Likewise.
* config/rs6000/t-fprules (MULTILIB_MATCHES_FLOAT): Include -mcpu=476.
* config/rs6000/rs6000.c (processor_costs): Add ppc476_cost.
(processor_target_table): Add 476 and 476fp entries.
(rs6000_override_options): Use ppc476_cost for PROCESSOR_PPC476.
(rs6000_issue_rate): Add CPU_PPC476.
* config/rs6000/rs6000.h (ASM_CPU_476_SPEC): Define.
(ASM_CPU_SPEC): Pass %(asm_cpu_476) for -mcpu=476 and -mcpu=476fp.
(processor_type): Add PROCESSOR_PPC476.
(EXTRA_SPECS): Add asm_cpu_476 string.
* config/rs6000/rs6000.md: (define_attr "type"): Add isel attribute.
(define_attr "cpu"): Add ppc476.
Include 476.md.
Update comments for 476.
(isel_signed, isel_unsigned): Change to use "isel" type attribute.
* config/rs6000/vxworks.h (CPP_SPEC): Handle 464 and 476.
Update copyright year.
* config/rs6000/476.md: New file.
* config/rs6000/40x.md: Add description for "isel" attribute.
Update copyright year.
* config/rs6000/440.md: Likewise.
* config/rs6000/603.md: Likewise.
* config/rs6000/6xx.md: Likewise.
* config/rs6000/7450.md: Likewise.
* config/rs6000/7xx.md: Likewise.
* config/rs6000/8540.md: Likewise.
* config/rs6000/cell.md: Likewise.
* config/rs6000/e300c2c3.md: Likewise.
* config/rs6000/e500mc.md: Likewise.
* config/rs6000/mpc.md: Likewise.
* config/rs6000/power4.md: Likewise.
* config/rs6000/power5.md: Likewise.
* config/rs6000/power6.md: Likewise.
* config/rs6000/power7.md: Likewise.
* config/rs6000/rios1.md: Likewise.
* config/rs6000/rios2.md: Likewise.
* config/rs6000/rs64.md: Likewise.
From-SVN: r152626
Diffstat (limited to 'gcc/doc')
-rw-r--r-- | gcc/doc/invoke.texi | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index da7afea..3f131fd 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14606,9 +14606,9 @@ Set architecture type, register usage, choice of mnemonics, and instruction scheduling parameters for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{464}, @samp{464fp}, -@samp{505}, @samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604}, -@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400}, -@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823}, +@samp{476}, @samp{476fp}, @samp{505}, @samp{601}, @samp{602}, @samp{603}, +@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740}, +@samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823}, @samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2}, @samp{e300c3}, @samp{e500mc}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3}, @samp{power4}, @@ -14954,7 +14954,7 @@ hardware floating is used. @opindex mmulhw @opindex mno-mulhw Generate code that uses (does not use) the half-word multiply and -multiply-accumulate instructions on the IBM 405, 440 and 464 processors. +multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. These instructions are generated by default when targetting those processors. @@ -14963,7 +14963,7 @@ processors. @opindex mdlmzb @opindex mno-dlmzb Generate code that uses (does not use) the string-search @samp{dlmzb} -instruction on the IBM 405, 440 and 464 processors. This instruction is +instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targetting those processors. @item -mno-bit-align |