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author | Matthew Fortune <matthew.fortune@mips.com> | 2018-06-13 20:40:28 +0000 |
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committer | Robert Suchanek <rts@gcc.gnu.org> | 2018-06-13 20:40:28 +0000 |
commit | 30c0ee9ca68e62a066f2653da11c50f708666857 (patch) | |
tree | eb64925dcae8e0e75f32d31b1b8b35f896611627 /gcc/doc | |
parent | 1df5fce42a295ae8cb34c6a4aae30814679b0b59 (diff) | |
download | gcc-30c0ee9ca68e62a066f2653da11c50f708666857.zip gcc-30c0ee9ca68e62a066f2653da11c50f708666857.tar.gz gcc-30c0ee9ca68e62a066f2653da11c50f708666857.tar.bz2 |
MIPS: Add support for P6600.
gcc/ChangeLog:
2018-06-13 Matthew Fortune <matthew.fortune@mips.com>
Prachi Godbole <prachi.godbole@imgtec.com>
* config/mips/mips-cpus.def: Define P6600.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/mips.c (mips_ucbranch_type): New enum.
(mips_rtx_cost_data): Add support for P6600.
(mips_issue_rate): Likewise.
(mips_multipass_dfa_lookahead): Likewise.
(mips_avoid_hazard): Likewise.
(mips_reorg_process_insns): Likewise.
(mips_classify_branch_p6600): New function.
* config/mips/mips.h (TUNE_P6600): New define.
(MIPS_ISA_LEVEL_SPEC): Infer mips64r6 from p6600.
(ENABLE_LD_ST_PAIRS): Enable load/store bonding for p6600.
* config/mips/mips.md: Include p6600.md.
(processor): Add p6600.
* config/mips/p6600.md: New file.
* doc/invoke.texi: Add p6600 to supported architectures.
Co-Authored-By: Prachi Godbole <prachi.godbole@imgtec.com>
From-SVN: r261570
Diffstat (limited to 'gcc/doc')
-rw-r--r-- | gcc/doc/invoke.texi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index eb33b56..940b846 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20112,7 +20112,7 @@ The processor names are: @samp{m5100}, @samp{m5101}, @samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{octeon3}, @samp{orion}, -@samp{p5600}, +@samp{p5600}, @samp{p6600}, @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400}, @samp{r4600}, @samp{r4650}, @samp{r4700}, @samp{r6000}, @samp{r8000}, @samp{rm7000}, @samp{rm9000}, |