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| author | Andrea Corallo <andrea.corallo@arm.com> | 2020-05-26 17:47:13 +0100 |
|---|---|---|
| committer | Andrea Corallo <andrea.corallo@arm.com> | 2020-07-10 13:20:34 +0200 |
| commit | d2ed233cb940aa3eecc163d98b47979dd81dbc0a (patch) | |
| tree | f24fa6e52fba1ed1cd9312fe5d569c5896b0eb67 /gcc/doc | |
| parent | c4fc6a3e0a209e01d0f223ca9987f93083f89882 (diff) | |
| download | gcc-d2ed233cb940aa3eecc163d98b47979dd81dbc0a.zip gcc-d2ed233cb940aa3eecc163d98b47979dd81dbc0a.tar.gz gcc-d2ed233cb940aa3eecc163d98b47979dd81dbc0a.tar.bz2 | |
arm: Implement Armv8.1-M low overhead loops
gcc/ChangeLog
2020-06-18 Andrea Corallo <andrea.corallo@arm.com>
Mihail-Calin Ionescu <mihail.ionescu@arm.com>
Iain Apreotesei <iain.apreotesei@arm.com>
* config/arm/arm-protos.h (arm_target_insn_ok_for_lob): New
prototype.
* config/arm/arm.c (TARGET_INVALID_WITHIN_DOLOOP): Define.
(arm_invalid_within_doloop): Implement invalid_within_doloop hook.
(arm_target_insn_ok_for_lob): New function.
* config/arm/arm.h (TARGET_HAVE_LOB): Define macro.
* config/arm/thumb2.md (*doloop_end_internal, doloop_begin)
(dls_insn): Add new patterns.
(doloop_end): Modify to select LR when LOB is available.
* config/arm/unspecs.md: Add new unspec.
* doc/sourcebuild.texi (arm_v8_1_lob_ok)
(arm_thumb2_ok_no_arm_v8_1_lob): Document new target supports
options.
gcc/testsuite/ChangeLog
2020-06-18 Andrea Corallo <andrea.corallo@arm.com>
Mihail-Calin Ionescu <mihail.ionescu@arm.com>
Iain Apreotesei <iain.apreotesei@arm.com>
* gcc.target/arm/lob.h: New header.
* gcc.target/arm/lob1.c: New testcase.
* gcc.target/arm/lob2.c: Likewise.
* gcc.target/arm/lob3.c: Likewise.
* gcc.target/arm/lob4.c: Likewise.
* gcc.target/arm/lob5.c: Likewise.
* gcc.target/arm/lob6.c: Likewise.
* gcc.target/arm/unsigned-extend-2.c: Do not run when generating
low loop overhead.
* gcc.target/arm/ivopts.c: Fix check for low loop overhead.
* lib/target-supports.exp (check_effective_target_arm_v8_1_lob)
(check_effective_target_arm_thumb2_ok_no_arm_v8_1_lob): New procs.
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/sourcebuild.texi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 5b5b845..9f37ac2 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2009,6 +2009,17 @@ ARM target supports the @code{-mfloat-abi=softfp} option. @anchor{arm_hard_ok} ARM target supports the @code{-mfloat-abi=hard} option. +@item arm_v8_1_lob_ok +@anchor{arm_v8_1_lob_ok} +ARM Target supports executing the Armv8.1-M Mainline Low Overhead Loop +instructions @code{DLS} and @code{LE}. +Some multilibs may be incompatible with these options. + +@item arm_thumb2_ok_no_arm_v8_1_lob +ARM target generates Thumb-2 code for @code{-mthumb} but does not +support executing the Armv8.1-M Mainline Low Overhead Loop +instructions @code{DLS} and @code{LE}. + @end table @subsubsection AArch64-specific attributes |