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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-07-19 11:24:31 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-07-19 11:24:31 +0000 |
| commit | c10abf530e52972ef708f6e72cf20dd920cd22a2 (patch) | |
| tree | 4247b9e7fc4f9dd7b86d7524951f84aac28e3c1e /gcc/doc | |
| parent | 14298fa4891ee9b347d7f286cc8ef266976f9e18 (diff) | |
| download | gcc-c10abf530e52972ef708f6e72cf20dd920cd22a2.zip gcc-c10abf530e52972ef708f6e72cf20dd920cd22a2.tar.gz gcc-c10abf530e52972ef708f6e72cf20dd920cd22a2.tar.bz2 | |
[AArch64] Rename +bitperm to +sve2-bitperm
After some discussion, we've decided to rename the +bitperm feature
flag to +sve2-bitperm, so that it's consistent with the other SVE2
feature flags. The associated macro was already
__ARM_FEATURE_SVE2_BITPERM, so only the feature flag itself
needs to change.
2019-07-19 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* doc/invoke.texi: Rename the AArch64 +bitperm extension flag
to +sve-bitperm.
* config/aarch64/aarch64-option-extensions.def: Likewise.
From-SVN: r273600
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 758aef3..b887f5f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -16083,7 +16083,7 @@ not affect code generation. This option is enabled by default for @item sve2 Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE instructions. -@item bitperm +@item sve2-bitperm Enable SVE2 bitperm instructions. This also enables SVE2 instructions. @item sve2-sm4 Enable SVE2 sm4 instructions. This also enables SVE2 instructions. |