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| author | Jakub Jelinek <jakub@redhat.com> | 2019-06-19 12:00:04 +0200 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2019-06-19 12:00:04 +0200 |
| commit | 2e83f583c27ef7a9d3b0fb0b5ed372439d6222a8 (patch) | |
| tree | 34682e23ea4f37c5d4665d95460d04025ea317b3 /gcc/doc | |
| parent | 6a2892a6d3aef8a1ce26386d626f26e6100099f6 (diff) | |
| download | gcc-2e83f583c27ef7a9d3b0fb0b5ed372439d6222a8.zip gcc-2e83f583c27ef7a9d3b0fb0b5ed372439d6222a8.tar.gz gcc-2e83f583c27ef7a9d3b0fb0b5ed372439d6222a8.tar.bz2 | |
md.texi: Document vec_shl_<mode> pattern.
* doc/md.texi: Document vec_shl_<mode> pattern.
* optabs.def (vec_shl_optab): New optab.
* optabs.c (shift_amt_for_vec_perm_mask): Add shift_optab
argument, if == vec_shl_optab, check for left whole vector shift
pattern rather than right shift.
(expand_vec_perm_const): Add vec_shl_optab support.
* optabs-query.c (can_vec_perm_var_p): Mention also vec_shl optab
in the comment.
* tree-vect-generic.c (lower_vec_perm): Support permutations which
can be handled by vec_shl_optab.
* tree-vect-stmts.c (scan_store_can_perm_p): New function.
(check_scan_store): Use it.
(vectorizable_scan_store): If target can't do normal permutations,
try to use whole vector left shifts and if needed a VEC_COND_EXPR
after it.
* config/i386/sse.md (vec_shl_<mode>): New expander.
* gcc.dg/vect/vect-simd-8.c: If main is defined, don't include
tree-vect.h nor call check_vect.
* gcc.dg/vect/vect-simd-9.c: Likewise.
* gcc.dg/vect/vect-simd-10.c: New test.
* gcc.target/i386/sse2-vect-simd-8.c: New test.
* gcc.target/i386/sse2-vect-simd-9.c: New test.
* gcc.target/i386/sse2-vect-simd-10.c: New test.
* gcc.target/i386/avx2-vect-simd-8.c: New test.
* gcc.target/i386/avx2-vect-simd-9.c: New test.
* gcc.target/i386/avx2-vect-simd-10.c: New test.
* gcc.target/i386/avx512f-vect-simd-8.c: New test.
* gcc.target/i386/avx512f-vect-simd-9.c: New test.
* gcc.target/i386/avx512f-vect-simd-10.c: New test.
From-SVN: r272472
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/md.texi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 40c2b8b..b45b4be 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5459,6 +5459,14 @@ in operand 2. Store the result in vector output operand 0. Operands 0 and 1 have mode @var{m} and operand 2 has the mode appropriate for one element of @var{m}. +@cindex @code{vec_shl_@var{m}} instruction pattern +@item @samp{vec_shl_@var{m}} +Whole vector left shift in bits, i.e.@: away from element 0. +Operand 1 is a vector to be shifted. +Operand 2 is an integer shift amount in bits. +Operand 0 is where the resulting shifted vector is stored. +The output and input vectors should have the same modes. + @cindex @code{vec_shr_@var{m}} instruction pattern @item @samp{vec_shr_@var{m}} Whole vector right shift in bits, i.e.@: towards element 0. |