Remove bt-load.c

bt-load.c has AFAIK been dead code since the removal of the SH5 port
in 2016.  I have a patch series that would need to update the liveness
tracking in a nontrivial way, so it seemed better to remove the pass
rather than install an untested and probably bogus change.

2019-09-09  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* Makefile.in (OBJS): Remove bt-load.o.
	* doc/invoke.texi (fbranch-target-load-optimize): Delete.
	(fbranch-target-load-optimize2, fbtr-bb-exclusive): Likewise.
	* common.opt (fbranch-target-load-optimize): Mark as Ignore and
	document that the option no longer does anything.
	(fbranch-target-load-optimize2, fbtr-bb-exclusive): Likewise.
	* target.def (branch_target_register_class): Delete.
	(branch_target_register_callee_saved): Likewise.
	* doc/tm.texi.in (TARGET_BRANCH_TARGET_REGISTER_CLASS): Likewise.
	(TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED): Likewise.
	* doc/tm.texi: Regenerate.
	* tree-pass.h (make_pass_branch_target_load_optimize1): Delete.
	(make_pass_branch_target_load_optimize2): Likewise.
	* passes.def (pass_branch_target_load_optimize1): Likewise.
	(pass_branch_target_load_optimize2): Likewise.
	* targhooks.h (default_branch_target_register_class): Likewise.
	* targhooks.c (default_branch_target_register_class): Likewise.
	* opt-suggestions.c (test_completion_valid_options): Remove
	-fbtr-bb-exclusive from the list of test options.
	* bt-load.c: Remove.

From-SVN: r275521

3 files changed, 1 insertions, 46 deletions

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 7bcdfcb..ef23a7d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -406,8 +406,7 @@ Objective-C and Objective-C++ Dialects}.
 -falign-loops[=@var{n}[:@var{m}:[@var{n2}[:@var{m2}]]]] @gol
 -fassociative-math  -fauto-profile  -fauto-profile[=@var{path}] @gol
 -fauto-inc-dec  -fbranch-probabilities @gol
--fbranch-target-load-optimize  -fbranch-target-load-optimize2 @gol
--fbtr-bb-exclusive  -fcaller-saves @gol
+-fcaller-saves @gol
 -fcombine-stack-adjustments  -fconserve-stack @gol
 -fcompare-elim  -fcprop-registers  -fcrossjumping @gol
 -fcse-follow-jumps  -fcse-skip-blocks  -fcx-fortran-rules @gol
@@ -11025,24 +11024,6 @@ locations inside a translation unit since the locations are unknown until
 link time.  An example of such an optimization is relaxing calls to short call
 instructions.
 
-@item -fbranch-target-load-optimize
-@opindex fbranch-target-load-optimize
-Perform branch target register load optimization before prologue / epilogue
-threading.
-The use of target registers can typically be exposed only during reload,
-thus hoisting loads out of loops and doing inter-block scheduling needs
-a separate optimization pass.
-
-@item -fbranch-target-load-optimize2
-@opindex fbranch-target-load-optimize2
-Perform branch target register load optimization after prologue / epilogue
-threading.
-
-@item -fbtr-bb-exclusive
-@opindex fbtr-bb-exclusive
-When performing branch target register load optimization, don't reuse
-branch target registers within any basic block.
-
 @item -fstdarg-opt
 @opindex fstdarg-opt
 Optimize the prologue of variadic argument functions with respect to usage of
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 0b5a08d..7bb8157 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -11755,28 +11755,6 @@ cannot_modify_jumps_past_reload_p ()
 @end smallexample
 @end deftypefn
 
-@deftypefn {Target Hook} reg_class_t TARGET_BRANCH_TARGET_REGISTER_CLASS (void)
-This target hook returns a register class for which branch target register
-optimizations should be applied.  All registers in this class should be
-usable interchangeably.  After reload, registers in this class will be
-re-allocated and loads will be hoisted out of loops and be subjected
-to inter-block scheduling.
-@end deftypefn
-
-@deftypefn {Target Hook} bool TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED (bool @var{after_prologue_epilogue_gen})
-Branch target register optimization will by default exclude callee-saved
-registers
-that are not already live during the current function; if this target hook
-returns true, they will be included.  The target code must than make sure
-that all target registers in the class returned by
-@samp{TARGET_BRANCH_TARGET_REGISTER_CLASS} that might need saving are
-saved.  @var{after_prologue_epilogue_gen} indicates if prologues and
-epilogues have already been generated.  Note, even if you only return
-true when @var{after_prologue_epilogue_gen} is false, you still are likely
-to have to make special provisions in @code{INITIAL_ELIMINATION_OFFSET}
-to reserve space for caller-saved target registers.
-@end deftypefn
-
 @deftypefn {Target Hook} bool TARGET_HAVE_CONDITIONAL_EXECUTION (void)
 This target hook returns true if the target supports conditional execution.
 This target hook is required only when the target has several different
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index a920055..e926c10 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -8001,10 +8001,6 @@ build_type_attribute_variant (@var{mdecl},
 
 @hook TARGET_CANNOT_MODIFY_JUMPS_P
 
-@hook TARGET_BRANCH_TARGET_REGISTER_CLASS
-
-@hook TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
-
 @hook TARGET_HAVE_CONDITIONAL_EXECUTION
 
 @hook TARGET_GEN_CCMP_FIRST