Add optabs for accelerating RAW and WAR alias checks

This patch adds optabs that check whether a read followed by a write
or a write followed by a read can be divided into interleaved byte
accesses without changing the dependencies between the bytes.
This is one of the uses of the SVE2 WHILERW and WHILEWR instructions.
(The instructions can also be used to limit the VF at runtime,
but that's future work.)

2019-11-18  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* doc/sourcebuild.texi (vect_check_ptrs): Document.
	* optabs.def (check_raw_ptrs_optab, check_war_ptrs_optab): New optabs.
	* doc/md.texi: Document them.
	* internal-fn.def (IFN_CHECK_RAW_PTRS, IFN_CHECK_WAR_PTRS): New
	internal functions.
	* internal-fn.h (internal_check_ptrs_fn_supported_p): Declare.
	* internal-fn.c (check_ptrs_direct): New macro.
	(expand_check_ptrs_optab_fn): Likewise.
	(direct_check_ptrs_optab_supported_p): Likewise.
	(internal_check_ptrs_fn_supported_p): New fuction.
	* tree-data-ref.c: Include internal-fn.h.
	(create_ifn_alias_checks): New function.
	(create_intersect_range_checks): Use it.
	* config/aarch64/iterators.md (SVE2_WHILE_PTR): New int iterator.
	(optab, cmp_op): Handle it.
	(raw_war, unspec): New int attributes.
	* config/aarch64/aarch64.md (UNSPEC_WHILERW, UNSPEC_WHILE_WR): New
	constants.
	* config/aarch64/predicates.md (aarch64_bytes_per_sve_vector_operand):
	New predicate.
	* config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): New
	expander.
	(@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): New
	pattern.

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_vect_check_ptrs):
	New procedure.
	* gcc.dg/vect/vect-alias-check-14.c: Expect IFN_CHECK_WAR to be
	used, if available.
	* gcc.dg/vect/vect-alias-check-15.c: Likewise.
	* gcc.dg/vect/vect-alias-check-16.c: Likewise IFN_CHECK_RAW.
	* gcc.target/aarch64/sve2/whilerw_1.c: New test.
	* gcc.target/aarch64/sve2/whilewr_1.c: Likewise.
	* gcc.target/aarch64/sve2/whilewr_2.c: Likewise.

From-SVN: r278414

2 files changed, 35 insertions, 0 deletions

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 87bbeb4..0ad4a00 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -5076,6 +5076,37 @@ for (i = 1; i < GET_MODE_NUNITS (@var{n}); i++)
   operand0[i] = operand0[i - 1] && (operand1 + i < operand2);
 @end smallexample
 
+@cindex @code{check_raw_ptrs@var{m}} instruction pattern
+@item @samp{check_raw_ptrs@var{m}}
+Check whether, given two pointers @var{a} and @var{b} and a length @var{len},
+a write of @var{len} bytes at @var{a} followed by a read of @var{len} bytes
+at @var{b} can be split into interleaved byte accesses
+@samp{@var{a}[0], @var{b}[0], @var{a}[1], @var{b}[1], @dots{}}
+without affecting the dependencies between the bytes.  Set operand 0
+to true if the split is possible and false otherwise.
+
+Operands 1, 2 and 3 provide the values of @var{a}, @var{b} and @var{len}
+respectively.  Operand 4 is a constant integer that provides the known
+common alignment of @var{a} and @var{b}.  All inputs have mode @var{m}.
+
+This split is possible if:
+
+@smallexample
+@var{a} == @var{b} || @var{a} + @var{len} <= @var{b} || @var{b} + @var{len} <= @var{a}
+@end smallexample
+
+You should only define this pattern if the target has a way of accelerating
+the test without having to do the individual comparisons.
+
+@cindex @code{check_war_ptrs@var{m}} instruction pattern
+@item @samp{check_war_ptrs@var{m}}
+Like @samp{check_raw_ptrs@var{m}}, but with the read and write swapped round.
+The split is possible in this case if:
+
+@smallexample
+@var{b} <= @var{a} || @var{a} + @var{len} <= @var{b}
+@end smallexample
+
 @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern
 @item @samp{vec_cmp@var{m}@var{n}}
 Output a vector comparison.  Operand 0 of mode @var{n} is the destination for
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index f3bf66c..a3432bc 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1487,6 +1487,10 @@ Target supports hardware vectors of @code{long}.
 @item vect_long_long
 Target supports hardware vectors of @code{long long}.
 
+@item vect_check_ptrs
+Target supports the @code{check_raw_ptrs} and @code{check_war_ptrs}
+optabs on vectors.
+
 @item vect_fully_masked
 Target supports fully-masked (also known as fully-predicated) loops,
 so that vector loops can handle partial as well as full vectors.