[ARM] Implement support for ACLE Coprocessor CDP intrinsics

gcc/ChangeLog:
2017-01-06  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/arm.md (<cdp>): New.
	* config/arm/arm.c (neon_const_bounds): Rename this ...
	(arm_const_bounds): ... this.
	(arm_coproc_builtin_available): New.
	* config/arm/arm-builtins.c (SIMD_MAX_BUILTIN_ARGS): Increase.
	(arm_type_qualifiers): Add 'qualifier_unsigned_immediate'.
	(CDP_QUALIFIERS): Define to...
	(arm_cdp_qualifiers): ... this. New.
	(void_UP): Define.
	(arm_expand_builtin_args): Add case for 6 arguments.
	* config/arm/arm-protos.h (neon_const_bounds): Rename this ...
	(arm_const_bounds): ... this.
	(arm_coproc_builtin_available): New.
	* config/arm/arm_acle.h (__arm_cdp): New.
	(__arm_cdp2): New.
	* config/arm/arm_acle_builtins.def (cdp): New.
	(cdp2): New.
	* config/arm/iterators.md (CDPI,CDP,cdp): New.
	* config/arm/neon.md: Rename all 'neon_const_bounds' to
	'arm_const_bounds'.
	* config/arm/types.md (coproc): New.
	* config/arm/unspecs.md (VUNSPEC_CDP, VUNSPEC_CDP2): New.
	* gcc/doc/extend.texi (ACLE): Add a mention of Coprocessor intrinsics.
	* gcc/doc/sourcebuild.texi (arm_coproc1_ok, arm_coproc2_ok,
	arm_coproc3_ok, arm_coproc4_ok): Document new effective targets.

gcc/testsuite/ChangeLog:
2017-01-06  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc.target/arm/acle/acle.exp: Run tests for different options
	and make sure fat-lto-objects is used such that we can still do
	assemble scans.
	* gcc.target/arm/acle/cdp.c: New.
	* gcc.target/arm/acle/cdp2.c: New.
	* lib/target-supports.exp (check_effective_target_arm_coproc1_ok): New.
	(check_effective_target_arm_coproc1_ok_nocache): New.
	(check_effective_target_arm_coproc2_ok): New.
	(check_effective_target_arm_coproc2_ok_nocache): New.
	(check_effective_target_arm_coproc3_ok): New.
	(check_effective_target_arm_coproc3_ok_nocache): New.
	(check_effective_target_arm_coproc4_ok): New.
	(check_effective_target_arm_coproc4_ok_nocache): New.

From-SVN: r244172

2 files changed, 22 insertions, 2 deletions

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 30bdcf0..e85da3a 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -12625,8 +12625,9 @@ The built-in intrinsics for the Advanced SIMD extension are available when
 NEON is enabled.
 
 Currently, ARM and AArch64 back ends do not support ACLE 2.0 fully.  Both
-back ends support CRC32 intrinsics from @file{arm_acle.h}.  The ARM back end's
-16-bit floating-point Advanced SIMD intrinsics currently comply to ACLE v1.1.
+back ends support CRC32 intrinsics and the ARM back end supports the
+Coprocessor intrinsics, all from @file{arm_acle.h}.  The ARM back end's 16-bit
+floating-point Advanced SIMD intrinsics currently comply to ACLE v1.1.
 AArch64's back end does not have support for 16-bit floating point Advanced SIMD
 intrinsics yet.
 
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 204518d..292a3c7 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1678,6 +1678,25 @@ div instruction.
 ARM target supports ARMv8-M Security Extensions, enabled by the @code{-mcmse}
 option.
 
+@item arm_coproc1_ok
+@anchor{arm_coproc1_ok}
+ARM target supports the following coprocessor instructions: @code{CDP},
+@code{LDC}, @code{STC}, @code{MCR} and @code{MRC}.
+
+@item arm_coproc2_ok
+@anchor{arm_coproc2_ok}
+ARM target supports all the coprocessor instructions also listed as supported
+in @ref{arm_coproc1_ok} in addition to the following: @code{CDP2}, @code{LDC2},
+@code{LDC2l}, @code{STC2}, @code{STC2l}, @code{MCR2} and @code{MRC2}.
+
+@item arm_coproc3_ok
+@anchor{arm_coproc3_ok}
+ARM target supports all the coprocessor instructions also listed as supported
+in @ref{arm_coproc2_ok} in addition the following: @code{MCRR} and @code{MRRC}.
+
+@item arm_coproc4_ok
+ARM target supports all the coprocessor instructions also listed as supported
+in @ref{arm_coproc3_ok} in addition the following: @code{MCRR2} and @code{MRRC2}.
 @end table
 
 @subsubsection AArch64-specific attributes