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| author | Tejas Joshi <TejasSanjay.Joshi@amd.com> | 2022-06-28 16:33:53 +0530 |
|---|---|---|
| committer | Venkataramanan Kumar <Venkataramanan.Kumar@amd.com> | 2022-10-21 15:25:57 +0530 |
| commit | bf3b532b524ecacb3202ab2c8af419ffaaab7cff (patch) | |
| tree | 0fbde96ab28f9269588ac179f880ca78e95ef4fb /gcc/doc | |
| parent | 88b34661f73e9da8032d20a37299223b39db4ef9 (diff) | |
| download | gcc-bf3b532b524ecacb3202ab2c8af419ffaaab7cff.zip gcc-bf3b532b524ecacb3202ab2c8af419ffaaab7cff.tar.gz gcc-bf3b532b524ecacb3202ab2c8af419ffaaab7cff.tar.bz2 | |
Enable AMD znver4 support and add instruction reservations
2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com>
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver4.
* common/config/i386/i386-common.cc (processor_names): Add znver4.
(processor_alias_table): Add znver4 and modularize old znvers.
* common/config/i386/i386-cpuinfo.h (processor_subtypes):
AMDFAM19H_ZNVER4.
* config.gcc (x86_64-*-* |...): Likewise.
* config/i386/driver-i386.cc (host_detect_local_cpu): Let
-march=native recognize znver4 cpus.
* config/i386/i386-c.cc (ix86_target_macros_internal): Add znver4.
* config/i386/i386-options.cc (m_ZNVER4): New definition.
(m_ZNVER): Include m_ZNVER4.
(processor_cost_table): Add znver4.
* config/i386/i386.cc (ix86_reassociation_width): Likewise.
* config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER4.
(PTA_ZNVER1): New definition.
(PTA_ZNVER2): Likewise.
(PTA_ZNVER3): Likewise.
(PTA_ZNVER4): Likewise.
* config/i386/i386.md (define_attr "cpu"): Add znver4 and rename
md file.
* config/i386/x86-tune-costs.h (znver4_cost): New definition.
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver4.
(ix86_adjust_cost): Likewise.
* config/i386/znver1.md: Rename to znver.md.
* config/i386/znver.md: Add new reservations for znver4.
* doc/extend.texi: Add details about znver4.
* doc/invoke.texi: Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/funcspec-56.inc: Handle new march.
* g++.target/i386/mv29.C: Likewise.
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/extend.texi | 3 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 9 |
2 files changed, 12 insertions, 0 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index e2dbc1d..ba90bfa 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21935,6 +21935,9 @@ AMD Family 19h CPU. @item znver3 AMD Family 19h Zen version 3. +@item znver4 +AMD Family 19h Zen version 4. + @item x86-64 Baseline x86-64 microarchitecture level (as defined in x86-64 psABI). diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 4df2917..09548c4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -32172,6 +32172,15 @@ MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID, WBNOINVD, PKU, VPCLMULQDQ, VAES, and 64-bit instruction set extensions.) +@item znver4 +AMD Family 19h core based CPUs with x86-64 instruction set support. (This +supersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, +MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, +SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID, +WBNOINVD, PKU, VPCLMULQDQ, VAES, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD, +AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, AVX512VNNI, +AVX512BITALG, AVX512VPOPCNTDQ, GFNI and 64-bit instruction set extensions.) + @item btver1 CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit |