Support Intel prefetchit0/t1

gcc/ChangeLog:

	* common/config/i386/cpuinfo.h (get_available_features):
	Detect PREFETCHI.
	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_PREFETCHI_SET,
	OPTION_MASK_ISA2_PREFETCHI_UNSET): New.
	(ix86_handle_option): Handle -mprefetchi.
	* common/config/i386/i386-cpuinfo.h
	(enum processor_features): Add FEATURE_PREFETCHI.
	* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY
	for prefetchi.
	* config.gcc: Add prfchiintrin.h.
	* config/i386/cpuid.h (bit_PREFETCHI): New.
	* config/i386/i386-builtin-types.def:
	Add DEF_FUNCTION_TYPE (VOID, PCVOID, INT)
	and DEF_FUNCTION_TYPE (VOID, PCVOID, INT, INT, INT).
	* config/i386/i386-builtin.def (BDESC): Add new builtins.
	* config/i386/i386-c.cc (ix86_target_macros_internal):
	Define __PREFETCHI__.
	* config/i386/i386-expand.cc: Handle new builtins.
	* config/i386/i386-isa.def (PREFETCHI):
	Add DEF_PTA(PREFETCHI).
	* config/i386/i386-options.cc
	(ix86_valid_target_attribute_inner_p): Handle prefetchi.
	* config/i386/i386.md (prefetchi): New define_insn.
	* config/i386/i386.opt: Add option -mprefetchi.
	* config/i386/predicates.md (local_func_symbolic_operand):
	New predicates.
	* config/i386/x86gprintrin.h: Include prfchiintrin.h.
	* config/i386/xmmintrin.h (enum _mm_hint): New enum for
	prefetchi.
	(_mm_prefetch): Handle the highest bit of enum.
	* doc/extend.texi: Document prefetchi.
	* doc/invoke.texi: Document -mprefetchi.
	* doc/sourcebuild.texi: Document target prefetchi.
	* config/i386/prfchiintrin.h: New file.

gcc/testsuite/ChangeLog:

	* g++.dg/other/i386-2.C: Add -mprefetchi.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.target/i386/avx-1.c: Ditto.
	* gcc.target/i386/funcspec-56.inc: Add new target attribute.
	* gcc.target/i386/sse-13.c: Add -mprefetchi.
	* gcc.target/i386/sse-23.c: Ditto.
	* gcc.target/i386/x86gprintrin-1.c: Ditto.
	* gcc.target/i386/x86gprintrin-2.c: Ditto.
	* gcc.target/i386/x86gprintrin-3.c: Ditto.
	* gcc.target/i386/x86gprintrin-4.c: Ditto.
	* gcc.target/i386/x86gprintrin-5.c: Ditto.
	* gcc.target/i386/prefetchi-1.c: New test.
	* gcc.target/i386/prefetchi-2.c: Ditto.
	* gcc.target/i386/prefetchi-3.c: Ditto.
	* gcc.target/i386/prefetchi-4.c: Ditto.

Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>

3 files changed, 15 insertions, 3 deletions

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 8d4475f..ba1e12b 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7085,6 +7085,11 @@ Enable/disable the generation of the CMPccXADD instructions.
 @cindex @code{target("amx-fp16")} function attribute, x86
 Enable/disable the generation of the AMX-FP16 instructions.
 
+@item prefetchi
+@itemx no-prefetchi
+@cindex @code{target("prefetchi")} function attribute, x86
+Enable/disable the generation of the PREFETCHI instructions.
+
 @item cld
 @itemx no-cld
 @cindex @code{target("cld")} function attribute, x86
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 5077cd7..008a3c5 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1438,6 +1438,7 @@ See RS/6000 and PowerPC Options.
 -mrdseed  -msgx -mavx512vp2intersect -mserialize -mtsxldtrk@gol
 -mamx-tile  -mamx-int8  -mamx-bf16 -muintr -mhreset -mavxvnni@gol
 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 @gol
+-mprefetchi @gol
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops @gol
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg} @gol
 -mkl -mwidekl @gol
@@ -33012,6 +33013,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @need 200
 @itemx -mamx-fp16
 @opindex mamx-fp16
+@need 200
+@itemx -mprefetchi
+@opindex mprefetchi
 These switches enable the use of instructions in the MMX, SSE,
 SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF,
 AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
@@ -33022,9 +33026,9 @@ XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,
 GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
 ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
 UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512FP16,
-AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16 or CLDEMOTE extended
-instruction sets. Each has a corresponding @option{-mno-} option to disable
-use of these instructions.
+AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI or CLDEMOTE
+extended instruction sets. Each has a corresponding @option{-mno-} option to
+disable use of these instructions.
 
 These extensions are also available as built-in functions: see
 @ref{x86 Built-in Functions}, for details of the functions enabled and
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 17a6f21..055a766 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2532,6 +2532,9 @@ Target does not require strict alignment.
 @item pie_copyreloc
 The x86-64 target linker supports PIE with copy reloc.
 
+@item prefetchi
+Target supports the execution of @code{prefetchi} instructions.
+
 @item rdrand
 Target supports x86 @code{rdrand} instruction.