Support Intel RAO-INT

gcc/ChangeLog:

	* common/config/i386/cpuinfo.h (get_available_features):
	Detect raoint.
	* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_RAOINT_SET,
	OPTION_MASK_ISA2_RAOINT_UNSET): New.
	(ix86_handle_option): Handle -mraoint.
	* common/config/i386/i386-cpuinfo.h (enum processor_features):
	Add FEATURE_RAOINT.
	* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
	raoint.
	* config.gcc: Add raointintrin.h
	* config/i386/cpuid.h (bit_RAOINT): New.
	* config/i386/i386-builtin.def (BDESC): Add new builtins.
	* config/i386/i386-c.cc (ix86_target_macros_internal): Define
	__RAOINT__.
	* config/i386/i386-isa.def (RAOINT): Add DEF_PTA(RAOINT).
	* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
	Add -mraoint.
	* config/i386/sync.md (rao_a<raointop><mode>): New define insn.
	* config/i386/i386.opt: Add option -mraoint.
	* config/i386/x86gprintrin.h: Include raointintrin.h.
	* doc/extend.texi: Document raoint.
	* doc/invoke.texi: Document -mraoint.
	* doc/sourcebuild.texi: Document target raoint.
	* config/i386/raointintrin.h: New file.

gcc/testsuite/ChangeLog:

	* g++.dg/other/i386-2.C: Add -mraoint.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.target/i386/funcspec-56.inc: Add new target attribute.
	* gcc.target/i386/sse-12.c: Add -mraoint.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Add raoint target.
	* gcc.target/i386/sse-23.c: Ditto.
	* lib/target-supports.exp: Add check_effective_target_raoint.
	* gcc.target/i386/rao-helper.h: New test.
	* gcc.target/i386/raoint-1.c: Ditto.
	* gcc.target/i386/raoint-aadd-2.c: Ditto.
	* gcc.target/i386/raoint-aand-2.c: Ditto.
	* gcc.target/i386/raoint-aor-2.c: Ditto.
	* gcc.target/i386/raoint-axor-2.c: Ditto.
	* gcc.target/i386/x86gprintrin-1.c: Ditto.
	* gcc.target/i386/x86gprintrin-2.c: Ditto.
	* gcc.target/i386/x86gprintrin-3.c: Ditto.
	* gcc.target/i386/x86gprintrin-4.c: Ditto.
	* gcc.target/i386/x86gprintrin-5.c: Ditto.

3 files changed, 15 insertions, 4 deletions

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 8ac9f91..33a4933 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7090,6 +7090,11 @@ Enable/disable the generation of the AMX-FP16 instructions.
 @cindex @code{target("prefetchi")} function attribute, x86
 Enable/disable the generation of the PREFETCHI instructions.
 
+@item raoint
+@itemx no-raoint
+@cindex @code{target("raoint")} function attribute, x86
+Enable/disable the generation of the RAOINT instructions.
+
 @item cld
 @itemx no-cld
 @cindex @code{target("cld")} function attribute, x86
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c9ff5b0..7417f52 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1438,7 +1438,7 @@ See RS/6000 and PowerPC Options.
 -mrdseed  -msgx -mavx512vp2intersect -mserialize -mtsxldtrk@gol
 -mamx-tile  -mamx-int8  -mamx-bf16 -muintr -mhreset -mavxvnni@gol
 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 @gol
--mprefetchi @gol
+-mprefetchi -mraoint @gol
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops @gol
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg} @gol
 -mkl -mwidekl @gol
@@ -33027,6 +33027,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @need 200
 @itemx -mprefetchi
 @opindex mprefetchi
+@need 200
+@itemx -mraoint
+@opindex mraoint
 These switches enable the use of instructions in the MMX, SSE,
 SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF,
 AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
@@ -33037,9 +33040,9 @@ XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,
 GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
 ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
 UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512FP16,
-AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI or CLDEMOTE
-extended instruction sets. Each has a corresponding @option{-mno-} option to
-disable use of these instructions.
+AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT or
+CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-}
+option to disable use of these instructions.
 
 These extensions are also available as built-in functions: see
 @ref{x86 Built-in Functions}, for details of the functions enabled and
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 055a766..7662669 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2535,6 +2535,9 @@ The x86-64 target linker supports PIE with copy reloc.
 @item prefetchi
 Target supports the execution of @code{prefetchi} instructions.
 
+@item raoint
+Target supports the execution of @code{raoint} instructions.
+
 @item rdrand
 Target supports x86 @code{rdrand} instruction.