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| author | Monk Chiang <monk.chiang@sifive.com> | 2024-02-01 17:14:18 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2024-02-01 20:38:15 +0800 |
| commit | 5c18df44fd1387653595869c9145c63fffb8cfac (patch) | |
| tree | 9a991a8d10897f2fbf2e39dc93587e123b3df601 /gcc/doc | |
| parent | 099d53e5b5404532e8910d1430f3942c4f07976c (diff) | |
| download | gcc-5c18df44fd1387653595869c9145c63fffb8cfac.zip gcc-5c18df44fd1387653595869c9145c63fffb8cfac.tar.gz gcc-5c18df44fd1387653595869c9145c63fffb8cfac.tar.bz2 | |
RISC-V: Add minimal support for 7 new unprivileged extensions
The RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
These extensions don't add any new features but
describe existing features. So this patch only adds parsing.
Za64rs: Reservation set size of 64 bytes
Za128rs: Reservation set size of 128 bytes
Ziccif: Main memory supports instruction fetch with atomicity requirement
Ziccrse: Main memory supports forward progress on LR/SC sequences
Ziccamoa: Main memory supports all atomics in A
Zicclsm: Main memory supports misaligned loads/stores
Zic64b: Cache block size isf 64 bytes
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
* config/riscv/riscv.opt: New macro for 7 new unprivileged
extensions.
* doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/za-ext.c: New test.
* gcc.target/riscv/zi-ext.c: New test.
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ca2c0e9..09abd2a 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30262,6 +30262,14 @@ Supported extension are listed below: @tab 1.0 @tab Integer conditional operations extension. +@item za64rs +@tab 1.0 +@tab Reservation set size of 64 bytes. + +@item za128rs +@tab 1.0 +@tab Reservation set size of 128 bytes. + @item zawrs @tab 1.0 @tab Wait-on-reservation-set extension. @@ -30370,6 +30378,26 @@ Supported extension are listed below: @tab 1.0 @tab Cache-block prefetch extension. +@item zic64b +@tab 1.0 +@tab Cache block size isf 64 bytes. + +@item ziccamoa +@tab 1.0 +@tab Main memory supports all atomics in A. + +@item ziccif +@tab 1.0 +@tab Main memory supports instruction fetch with atomicity requirement. + +@item zicclsm +@tab 1.0 +@tab Main memory supports misaligned loads/stores. + +@item ziccrse +@tab 1.0 +@tab Main memory supports forward progress on LR/SC sequences. + @item zicntr @tab 2.0 @tab Standard extension for base counters and timers. |