aboutsummaryrefslogtreecommitdiff
path: root/gcc/doc
diff options
context:
space:
mode:
authorRichard Henderson <rth@redhat.com>2004-12-22 23:58:41 -0800
committerRichard Henderson <rth@gcc.gnu.org>2004-12-22 23:58:41 -0800
commit1e0598e25c07970f830bb52f2ae75c7007dea4b4 (patch)
tree82224c10b6b040c1b09d8cc1ee0b14eb54d26e72 /gcc/doc
parent1c47af84a30650b28b6d1957f1689e2107396a2e (diff)
downloadgcc-1e0598e25c07970f830bb52f2ae75c7007dea4b4.zip
gcc-1e0598e25c07970f830bb52f2ae75c7007dea4b4.tar.gz
gcc-1e0598e25c07970f830bb52f2ae75c7007dea4b4.tar.bz2
optabs.h (OTI_movmisalign, [...]): New.
* optabs.h (OTI_movmisalign, movmisalign_optab): New. * optabs.c (init_optabs): Create it. * genopinit.c (optabs): Initialize it. * expr.c (expand_expr_real_1) <MISALIGNED_INDIRECT_REF>: Use it. * tree-vectorizer.c (vect_supportable_dr_alignment): Likewise. * target-def.h (TARGET_VECTORIZE_MISALIGNED_MEM_OK): Remove. * target.h (vectorize.misaligned_mem_ok): Remove. * targhooks.c (default_vect_misaligned_mem_ok): Remove. * doc/md.texi (movmisalign): New. * doc/tm.texi (TARGET_VECTORIZE_MISALIGNED_MEM_OK): Remove. From-SVN: r92537
Diffstat (limited to 'gcc/doc')
-rw-r--r--gcc/doc/md.texi11
-rw-r--r--gcc/doc/tm.texi10
2 files changed, 11 insertions, 10 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 36c73a1..2c41bc4 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2758,6 +2758,17 @@ with mode @var{m} of a register whose natural mode is wider,
the @samp{movstrict@var{m}} instruction is guaranteed not to alter
any of the register except the part which belongs to mode @var{m}.
+@cindex @code{movmisalign@var{m}} instruction pattern
+@item @samp{movmisalign@var{m}}
+This variant of a move pattern is designed to load or store a value
+from a memory address that is not naturally aligned for its mode.
+For a store, the memory will be in operand 0; for a load, the memory
+will be in operand 1. The other operand is guaranteed not to be a
+memory, so that it's easy to tell whether this is a load or store.
+
+This pattern is used by the autovectorizer, and when expanding a
+@code{MISALIGNED_INDIRECT_REF} expression.
+
@cindex @code{load_multiple} instruction pattern
@item @samp{load_multiple}
Load several consecutive memory locations into consecutive registers.
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index e338442..fb45a6c 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -5184,16 +5184,6 @@ holding the constant. This restriction is often true of addresses
of TLS symbols for various targets.
@end deftypefn
-@deftypefn {Target Hook} bool TARGET_VECTORIZE_MISALIGNED_MEM_OK (@var{mode})
-This hook should return true if a move* pattern to/from memory
-can be generated for machine_mode @var{mode} even if the memory location
-is unaligned.
-If a move* of data to/from unaligned memory locations is not supported for
-machine_mode @var{mode}, the hook should return false.
-This hook is used by the autovectorizer, and when expanding a
-@code{MISALIGNED_INDIRECT_REF} expression.
-@end deftypefn
-
@deftypefn {Target Hook} tree TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD (void)
This hook should return the DECL of a function @var{f} that given an
address @var{addr} as an argument returns a mask @var{m} that can be