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| author | Geoffrey Keating <geoffk@redhat.com> | 2001-08-19 21:40:37 +0000 |
|---|---|---|
| committer | Geoffrey Keating <geoffk@gcc.gnu.org> | 2001-08-19 21:40:37 +0000 |
| commit | 13fac94a68a4da815faa73d6a457c3d9d3bf94f5 (patch) | |
| tree | d870f65f83d3ef830ed1c114ba9b46e221c555ed /gcc/doc | |
| parent | 915a17f667e9abdfddbc8b429ff29db1becacdbb (diff) | |
| download | gcc-13fac94a68a4da815faa73d6a457c3d9d3bf94f5.zip gcc-13fac94a68a4da815faa73d6a457c3d9d3bf94f5.tar.gz gcc-13fac94a68a4da815faa73d6a457c3d9d3bf94f5.tar.bz2 | |
invoke.texi (MIPS Options): Document -mfused-madd.
* doc/invoke.texi (MIPS Options): Document -mfused-madd.
* config/mips/mips.h (MASK_NO_FUSED_MADD): New.
(TARGET_FUSED_MADD): New.
(TARGET_SWITCHES): Add -mfused-madd, -mno-fused-madd.
* config/mips/mips.md: Add TARGET_FUSED_MADD as condition to
the multiply-add instructions.
From-SVN: r45041
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 67c25c0..c0e69e6 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -450,7 +450,8 @@ in the following sections. @gccoptlist{ -mabicalls -march=@var{cpu-type} -mtune=@var{cpu=type} @gol -mcpu=@var{cpu-type} -membedded-data -muninit-const-in-rodata @gol --membedded-pic -mfp32 -mfp64 -mgas -mgp32 -mgp64 @gol +-membedded-pic -mfp32 -mfp64 -mfused-madd -mno-fused-madd @gol +-mgas -mgp32 -mgp64 @gol -mgpopt -mhalf-pic -mhard-float -mint64 -mips1 @gol -mips2 -mips3 -mips4 -mlong64 -mlong32 -mlong-calls -mmemcpy @gol -mmips-as -mmips-tfile -mno-abicalls @gol @@ -7080,6 +7081,18 @@ the default. Assume that 32 64-bit floating point registers are available. This is the default when the @option{-mips3} option is used. +@item -mfused-madd +@itemx -mno-fused-madd +@opindex mfused-madd +@opindex mno-fused-madd +Generate code that uses (does not use) the floating point multiply and +accumulate instructions, when they are available. These instructions +are generated by default if they are available, but this may be +undesirable if the extra precision causes problems or on certain chips +in the mode where denormals are rounded to zero where denormals +generated by multiply and accumulate instructions cause exceptions +anyway. + @item -mgp32 @opindex mgp32 Assume that 32 32-bit general purpose registers are available. This is |