gcc/

	* doc/md.texi (extv@var{m}, extvmisalign@var{m}, extzv@var{m})
	(extzvmisalign@var{m}, insv@var{m}, insvmisalign@var{m}): Document.
	(insv, extv, extzv): Deprecate.
	* optabs.def (insv_optab, extv_optab, extzv_optab)
	(insvmisalign_optab, extvmisalign_optab, extzvmisalign_optab):
	New optabs.
	* optabs.c (get_optab_extraction_insn): New function.
	(get_extraction_insn): Use it.
	* config/mips/mips.md (extv): Split into...
	(extvmisalign<mode>, extv<mode>): ...these new patterns.  Rename
	existing extv<mode> pattern to...
	(*extv<mode>): ...this.
	(extzv): Split into...
	(extzvmisalign<mode>, extzv<mode>): ...these new patterns.  Rename
	existing extzv<mode> pattern to...
	(*extzv<mode>): ...this.
	(insv): Split into...
	(insvmisalign<mode>, insv<mode>): ...these new patterns.  Rename
	existing insv<mode> pattern to...
	(*insv<mode>): ...this.  Use const_int_operand rather than
	immediate_operand.
	* config/mips/mips.c (mips_block_move_straight): Use set_mem_size
	to set the size of BLKmode accesses.
	(mips_get_unaligned_mem): Require OP0 to be a BLKmode memory,
	turning it from an "rtx *" to an rtx.
	(mips_expand_ext_as_unaligned_load): Simplify for new optab
	interface.  Update call to mips_get_unaligned_mem.
	(mips_expand_ins_as_unaligned_store): Update call to
	mips_get_unaligned_mem.

From-SVN: r193606

1 files changed, 65 insertions, 0 deletions

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 396bf43..6c648ee 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -5294,6 +5294,62 @@ Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
 When overflows or underflows happen, the instruction saturates the
 results to the maximum or the minimum.
 
+@cindex @code{extv@var{m}} instruction pattern
+@item @samp{extv@var{m}}
+Extract a bit-field from register operand 1, sign-extend it, and store
+it in operand 0.  Operand 2 specifies the width of the field in bits
+and operand 3 the starting bit, which counts from the most significant
+bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
+otherwise.
+
+Operands 0 and 1 both have mode @var{m}.  Operands 2 and 3 have a
+target-specific mode.
+
+@cindex @code{extvmisalign@var{m}} instruction pattern
+@item @samp{extvmisalign@var{m}}
+Extract a bit-field from memory operand 1, sign extend it, and store
+it in operand 0.  Operand 2 specifies the width in bits and operand 3
+the starting bit.  The starting bit is always somewhere in the first byte of
+operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
+is true and from the least significant bit otherwise.
+
+Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
+Operands 2 and 3 have a target-specific mode.
+
+The instruction must not read beyond the last byte of the bit-field.
+
+@cindex @code{extzv@var{m}} instruction pattern
+@item @samp{extzv@var{m}}
+Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
+
+@cindex @code{extzvmisalign@var{m}} instruction pattern
+@item @samp{extzvmisalign@var{m}}
+Like @samp{extvmisalign@var{m}} except that the bit-field value is
+zero-extended.
+
+@cindex @code{insv@var{m}} instruction pattern
+@item @samp{insv@var{m}}
+Insert operand 3 into a bit-field of register operand 0.  Operand 1
+specifies the width of the field in bits and operand 2 the starting bit,
+which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
+is true and from the least significant bit otherwise.
+
+Operands 0 and 3 both have mode @var{m}.  Operands 1 and 2 have a
+target-specific mode.
+
+@cindex @code{insvmisalign@var{m}} instruction pattern
+@item @samp{insvmisalign@var{m}}
+Insert operand 3 into a bit-field of memory operand 0.  Operand 1
+specifies the width of the field in bits and operand 2 the starting bit.
+The starting bit is always somewhere in the first byte of operand 0;
+it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
+is true and from the least significant bit otherwise.
+
+Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
+Operands 1 and 2 have a target-specific mode.
+
+The instruction must not read or write beyond the last byte of the bit-field.
+
 @cindex @code{extv} instruction pattern
 @item @samp{extv}
 Extract a bit-field from operand 1 (a register or memory operand), where
@@ -5309,10 +5365,16 @@ for operands 2 and 3 and the constant is never zero for operand 2.
 The bit-field value is sign-extended to a full word integer
 before it is stored in operand 0.
 
+This pattern is deprecated; please use @samp{extv@var{m}} and
+@code{extvmisalign@var{m}} instead.
+
 @cindex @code{extzv} instruction pattern
 @item @samp{extzv}
 Like @samp{extv} except that the bit-field value is zero-extended.
 
+This pattern is deprecated; please use @samp{extzv@var{m}} and
+@code{extzvmisalign@var{m}} instead.
+
 @cindex @code{insv} instruction pattern
 @item @samp{insv}
 Store operand 3 (which must be valid for @code{word_mode}) into a
@@ -5324,6 +5386,9 @@ Operands 1 and 2 must be valid for @code{word_mode}.
 The RTL generation pass generates this instruction only with constants
 for operands 1 and 2 and the constant is never zero for operand 1.
 
+This pattern is deprecated; please use @samp{insv@var{m}} and
+@code{insvmisalign@var{m}} instead.
+
 @cindex @code{mov@var{mode}cc} instruction pattern
 @item @samp{mov@var{mode}cc}
 Conditionally move operand 2 or operand 3 into operand 0 according to the