RISC-V: Implement .SAT_TRUNC for vector unsigned int

This patch would like to implement the .SAT_TRUNC for the RISC-V
backend.  With the help of the RVV Vector Narrowing Fixed-Point
Clip Instructions.  The below SEW(S) are supported:

* e64 => e32
* e64 => e16
* e64 => e8
* e32 => e16
* e32 => e8
* e16 => e8

Take below example to see the changes to asm.
Form 1:
  #define DEF_VEC_SAT_U_TRUNC_FMT_1(NT, WT)                             \
  void __attribute__((noinline))                                        \
  vec_sat_u_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \
  {                                                                     \
    unsigned i;                                                         \
    for (i = 0; i < limit; i++)                                         \
      {                                                                 \
        WT x = in[i];                                                   \
        bool overflow = x > (WT)(NT)(-1);                               \
        out[i] = ((NT)x) | (NT)-overflow;                               \
      }                                                                 \
  }

DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t)

Before this patch:
.L3:
  vsetvli      a5,a2,e64,m1,ta,ma
  vle64.v      v1,0(a1)
  vmsgtu.vv    v0,v1,v2
  vsetvli      zero,zero,e32,mf2,ta,ma
  vncvt.x.x.w  v1,v1
  vmerge.vim   v1,v1,-1,v0
  vse32.v      v1,0(a0)
  slli         a4,a5,3
  add          a1,a1,a4
  slli         a4,a5,2
  add          a0,a0,a4
  sub          a2,a2,a5
  bne          a2,zero,.L3

After this patch:
.L3:
  vsetvli      a5,a2,e32,mf2,ta,ma
  vle64.v      v1,0(a1)
  vnclipu.wi   v1,v1,0
  vse32.v      v1,0(a0)
  slli         a4,a5,3
  add          a1,a1,a4
  slli         a4,a5,2
  add          a0,a0,a4
  sub          a2,a2,a5
  bne          a2,zero,.L3

Passed the rv64gcv fully regression tests.

gcc/ChangeLog:

	* config/riscv/autovec.md (ustrunc<mode><v_double_trunc>2): Add
	new pattern for double truncation.
	(ustrunc<mode><v_quad_trunc>2): Ditto but for quad truncation.
	(ustrunc<mode><v_oct_trunc>2): Ditto but for oct truncation.
	* config/riscv/riscv-protos.h (expand_vec_double_ustrunc): Add
	new func decl to expand double vec ustrunc.
	(expand_vec_quad_ustrunc): Ditto but for quad.
	(expand_vec_oct_ustrunc): Ditto but for oct.
	* config/riscv/riscv-v.cc (expand_vec_double_ustrunc): Add new
	func impl to expand vector double ustrunc.
	(expand_vec_quad_ustrunc): Ditto but for quad.
	(expand_vec_oct_ustrunc): Ditto but for oct.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
	test macros.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_data.h: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-3.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-4.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-5.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-6.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_unary_vv_run.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions