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authorCarl Love <cel@linux.ibm.com>2024-07-09 13:17:44 -0400
committerCarl Love <cel@linux.ibm.com>2024-07-09 13:34:41 -0400
commitb620845fff7d38bca3b79ca9f5a5d049eba9e7f8 (patch)
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parent6031e34af130d114a7a3de0108fdb39360e8b1b3 (diff)
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rs6000, extend the current vec_{un,}signed{e,o} built-ins
The built-ins __builtin_vsx_xvcvspsxds and __builtin_vsx_xvcvspuxds convert a vector of floats to a vector of signed/unsigned long long ints. Extend the existing vec_{un,}signed{e,o} built-ins to handle the argument vector of floats to return a vector of even/odd signed/unsigned integers. The define expands vsignede_v4sf, vsignedo_v4sf, vunsignede_v4sf, vunsignedo_v4sf are added to support the new vec_{un,}signed{e,o} built-ins. The built-ins __builtin_vsx_xvcvspsxds and __builtin_vsx_xvcvspuxds are now for internal use only. They are not documented and they do not have test cases. Add testcases and update documentation. gcc/ChangeLog: * config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvspsxds, __builtin_vsx_xvcvspuxds): Rename to __builtin_vsignede_v4sf, __builtin_vunsignede_v4sf respectively. (XVCVSPSXDS, XVCVSPUXDS): Rename to VEC_VSIGNEDE_V4SF, VEC_VUNSIGNEDE_V4SF respectively. (__builtin_vsignedo_v4sf, __builtin_vunsignedo_v4sf): New built-in definitions. * config/rs6000/rs6000-overload.def (vec_signede, vec_signedo, vec_unsignede, vec_unsignedo): Add new overloaded specifications. * config/rs6000/vsx.md (vsignede_v4sf, vsignedo_v4sf, vunsignede_v4sf, vunsignedo_v4sf): New define_expands. * doc/extend.texi (vec_signedo, vec_signede, vec_unsignedo, vec_unsignede): Add documentation for new overloaded built-ins to convert vector float to vector {un,}signed long long. gcc/testsuite/ChangeLog: * gcc.target/powerpc/builtins-3-runnable.c (test_unsigned_int_result, test_ll_unsigned_int_result): Add new argument. (vec_signede, vec_signedo, vec_unsignede, vec_unsignedo): New tests for the overloaded built-ins.
Diffstat (limited to 'gcc/doc')
-rw-r--r--gcc/doc/extend.texi10
1 files changed, 10 insertions, 0 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index b2e41a5..98e3966 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -22649,6 +22649,16 @@ if the VSX instruction set is available. The @samp{vec_vsx_ld} and
@samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X},
@samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
+@smallexample
+vector signed long long vec_signedo (vector float);
+vector signed long long vec_signede (vector float);
+vector unsigned long long vec_unsignedo (vector float);
+vector unsigned long long vec_unsignede (vector float);
+@end smallexample
+
+The overloaded built-ins @code{vec_signedo} and @code{vec_signede} are
+additional extensions to the built-ins as documented in the PVIPR.
+
@node PowerPC AltiVec Built-in Functions Available on ISA 2.07
@subsubsection PowerPC AltiVec Built-in Functions Available on ISA 2.07