ChangeLog: Follow spelling conventions.

	* ChangeLog: Follow spelling conventions.
	* ChangeLog.0: Likewise.
	* ChangeLog.1: Likewise.
	* ChangeLog.2: Likewise.
	* ChangeLog.4: Likewise.
	* ChangeLog.6: Likewise.
	* config.gcc: Likewise.
	* dwarfout.c: Likewise.
	* reload1.c: Likewise.
	* simplify-rtx.c: Likewise.
	* unwind-sjlj.c: Likewise.
	* config/avr/avr.h: Likewise.
	* config/d30v/d30v.h: Likewise.
	* config/frv/frv.c: Likewise.
	* config/frv/frv.h: Likewise.
	* config/ip2k/ip2k.h: Likewise.
	* config/m88k/m88k-move.sh: Likewise.
	* config/stormy16/stormy16.c: Likewise.
	* config/stormy16/stormy16.h: Likewise.
	* doc/extend.texi: Likewise.
	* doc/interface.texi: Likewise.
	* doc/invoke.texi: Likewise.
	* doc/md.texi: Likewise.
	* doc/rtl.texi: Likewise.
	* doc/tm.texi: Likewise.
	* doc/trouble.texi: Likewise.
	* ginclude/float.h: Likewise.
	* treelang/treelang.texi: Likewise.

From-SVN: r57179

7 files changed, 23 insertions, 23 deletions

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index e7d2ef7..e9fef25 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -3235,7 +3235,7 @@ typedef int more_aligned_int __attribute__ ((aligned (8)));
 @noindent
 force the compiler to insure (as far as it can) that each variable whose
 type is @code{struct S} or @code{more_aligned_int} will be allocated and
-aligned @emph{at least} on a 8-byte boundary.  On a Sparc, having all
+aligned @emph{at least} on a 8-byte boundary.  On a SPARC, having all
 variables of type @code{struct S} aligned to 8-byte boundaries allows
 the compiler to use the @code{ldd} and @code{std} (doubleword load and
 store) instructions when copying one variable of type @code{struct S} to
@@ -4140,7 +4140,7 @@ being used for other purposes in the preceding functions.
 Global register variables may not have initial values, because an
 executable file has no means to supply initial contents for a register.
 
-On the Sparc, there are reports that g3 @dots{} g7 are suitable
+On the SPARC, there are reports that g3 @dots{} g7 are suitable
 registers, but certain library functions, such as @code{getwd}, as well
 as the subroutines for division and remainder, modify g3 and g4.  g1 and
 g2 are local temporaries.
diff --git a/gcc/doc/interface.texi b/gcc/doc/interface.texi
index 846de56b..c554434 100644
--- a/gcc/doc/interface.texi
+++ b/gcc/doc/interface.texi
@@ -57,7 +57,7 @@ compiler for the system.  We may implement register argument passing on
 certain machines once we have a complete GNU system so that we can
 compile the libraries with GCC@.
 
-On some machines (particularly the Sparc), certain types of arguments
+On some machines (particularly the SPARC), certain types of arguments
 are passed ``by invisible reference''.  This means that the value is
 stored in memory, and the address of the memory location is passed to
 the subroutine.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 7751d58..80970f8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -3725,7 +3725,7 @@ in the output file.
 
 Use these options on systems where the linker can perform optimizations
 to improve locality of reference in the instruction space.  HPPA
-processors running HP-UX and Sparc processors running Solaris 2 have
+processors running HP-UX and SPARC processors running Solaris 2 have
 linkers with such optimizations.  Other systems using the ELF object format
 as well as AIX may have these optimizations in the future.
 
@@ -5363,7 +5363,7 @@ With @option{-mfaster-structs}, the compiler assumes that structures
 should have 8 byte alignment.  This enables the use of pairs of
 @code{ldd} and @code{std} instructions for copies in structure
 assignment, in place of twice as many @code{ld} and @code{st} pairs.
-However, the use of this changed alignment directly violates the Sparc
+However, the use of this changed alignment directly violates the SPARC
 ABI@.  Thus, it's intended only for use on targets where the developer
 acknowledges that their resulting code will not be directly in line with
 the rules of the ABI@.
@@ -5395,11 +5395,11 @@ They have been replaced with @option{-mcpu=xxx}.
 These two options select the processor for which the code is optimized.
 
 With @option{-mcypress} (the default), the compiler optimizes code for the
-Cypress CY7C602 chip, as used in the SparcStation/SparcServer 3xx series.
-This is also appropriate for the older SparcStation 1, 2, IPX etc.
+Cypress CY7C602 chip, as used in the SPARCStation/SPARCServer 3xx series.
+This is also appropriate for the older SPARCStation 1, 2, IPX etc.
 
-With @option{-msupersparc} the compiler optimizes code for the SuperSparc cpu, as
-used in the SparcStation 10, 1000 and 2000 series.  This flag also enables use
+With @option{-msupersparc} the compiler optimizes code for the SuperSPARC cpu, as
+used in the SPARCStation 10, 1000 and 2000 series.  This flag also enables use
 of the full SPARC v8 instruction set.
 
 These options are deprecated and will be deleted in a future GCC release.
@@ -10027,7 +10027,7 @@ loader is not part of GCC; it is part of the operating system).  If
 the GOT size for the linked executable exceeds a machine-specific
 maximum size, you get an error message from the linker indicating that
 @option{-fpic} does not work; in that case, recompile with @option{-fPIC}
-instead.  (These maximums are 16k on the m88k, 8k on the Sparc, and 32k
+instead.  (These maximums are 16k on the m88k, 8k on the SPARC, and 32k
 on the m68k and RS/6000.  The 386 has no such limit.)
 
 Position-independent code requires special support, and therefore works
@@ -10040,7 +10040,7 @@ position-independent.
 If supported for the target machine, emit position-independent code,
 suitable for dynamic linking and avoiding any limit on the size of the
 global offset table.  This option makes a difference on the m68k, m88k,
-and the Sparc.
+and the SPARC.
 
 Position-independent code requires special support, and therefore works
 only on certain machines.
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 3670341..db64075 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3480,7 +3480,7 @@ multiple condition registers, use a pseudo register.
 @findex next_cc0_user
 On some machines, the type of branch instruction generated may depend on
 the way the condition code was produced; for example, on the 68k and
-Sparc, setting the condition code directly from an add or subtract
+SPARC, setting the condition code directly from an add or subtract
 instruction does not clear the overflow bit the way that a test
 instruction does, so a different branch instruction must be used for
 some conditional branches.  For machines that use @code{(cc0)}, the set
@@ -3499,7 +3499,7 @@ different formats of the condition code register.
 Registers used to store the condition code value should have a mode that
 is in class @code{MODE_CC}.  Normally, it will be @code{CCmode}.  If
 additional modes are required (as for the add example mentioned above in
-the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
+the SPARC), define the macro @code{EXTRA_CC_MODES} to list the
 additional modes required (@pxref{Condition Code}).  Also define
 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
 
@@ -3511,7 +3511,7 @@ be specified at that time.
 If the cases that require different modes would be made by instruction
 combination, the macro @code{SELECT_CC_MODE} determines which machine
 mode should be used for the comparison result.  The patterns should be
-written using that mode.  To support the case of the add on the Sparc
+written using that mode.  To support the case of the add on the SPARC
 discussed above, we have the pattern
 
 @smallexample
@@ -3525,7 +3525,7 @@ discussed above, we have the pattern
   "@dots{}")
 @end smallexample
 
-The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
+The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
 for comparisons whose argument is a @code{plus}.
 
 @node Looping Patterns
diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
index 5a016be..1c9a4e4 100644
--- a/gcc/doc/rtl.texi
+++ b/gcc/doc/rtl.texi
@@ -1545,7 +1545,7 @@ preferable approach if only a small subset of instructions modify the
 condition code.  Other machines store condition codes in general
 registers; in such cases a pseudo register should be used.
 
-Some machines, such as the Sparc and RS/6000, have two sets of
+Some machines, such as the SPARC and RS/6000, have two sets of
 arithmetic instructions, one that sets and one that does not set the
 condition code.  This is best handled by normally generating the
 instruction that does not set the condition code, and making a pattern
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 8bc5155..6977f56 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -2410,7 +2410,7 @@ from memory or even from other types of registers.  An example is the
 from general registers, but not memory.  Some machines allow copying all
 registers to and from memory, but require a scratch register for stores
 to some memory locations (e.g., those with symbolic address on the RT,
-and those with certain symbolic address on the Sparc when compiling
+and those with certain symbolic address on the SPARC when compiling
 PIC)@.  In some cases, both an intermediate and a scratch register are
 required.
 
@@ -2790,7 +2790,7 @@ address of the stack word that points to the previous frame.
 @item SETUP_FRAME_ADDRESSES
 If defined, a C expression that produces the machine-specific code to
 setup the stack so that arbitrary frames can be accessed.  For example,
-on the Sparc, we must flush all of the register windows to the stack
+on the SPARC, we must flush all of the register windows to the stack
 before we can access arbitrary stack frames.  You will seldom need to
 define this macro.
 
@@ -5094,7 +5094,7 @@ automatically defined by @command{configure}, with value @samp{1}.
 @item SELECT_CC_MODE (@var{op}, @var{x}, @var{y})
 Returns a mode from class @code{MODE_CC} to be used when comparison
 operation code @var{op} is applied to rtx @var{x} and @var{y}.  For
-example, on the Sparc, @code{SELECT_CC_MODE} is defined as (see
+example, on the SPARC, @code{SELECT_CC_MODE} is defined as (see
 @pxref{Jump Patterns} for a description of the reason for this
 definition)
 
@@ -5138,7 +5138,7 @@ then @code{REVERSIBLE_CC_MODE (@var{mode})} must be zero.
 
 You need not define this macro if it would always returns zero or if the
 floating-point format is anything other than @code{IEEE_FLOAT_FORMAT}.
-For example, here is the definition used on the Sparc, where floating-point
+For example, here is the definition used on the SPARC, where floating-point
 inequality comparisons are always given @code{CCFPEmode}:
 
 @smallexample
diff --git a/gcc/doc/trouble.texi b/gcc/doc/trouble.texi
index 446fccc..d6ba632 100644
--- a/gcc/doc/trouble.texi
+++ b/gcc/doc/trouble.texi
@@ -163,7 +163,7 @@ Naturally, this does not happen when you use GCC@.
 You must specify all three options explicitly.
 
 @item
-On a Sparc, GCC aligns all values of type @code{double} on an 8-byte
+On a SPARC, GCC aligns all values of type @code{double} on an 8-byte
 boundary, and it expects every @code{double} to be so aligned.  The Sun
 compiler usually gives @code{double} values 8-byte alignment, with one
 exception: function arguments of type @code{double} may not be aligned.
@@ -202,7 +202,7 @@ Storing into the pointer can be done likewise with the same union.
 @item
 On Solaris, the @code{malloc} function in the @file{libmalloc.a} library
 may allocate memory that is only 4 byte aligned.  Since GCC on the
-Sparc assumes that doubles are 8 byte aligned, this may result in a
+SPARC assumes that doubles are 8 byte aligned, this may result in a
 fatal signal if doubles are stored in memory allocated by the
 @file{libmalloc.a} library.
 
@@ -219,7 +219,7 @@ when linking, compile and link against the file
 @file{mit/util/misc/dlsym.c} from the MIT version of X windows.
 
 @item
-The 128-bit long double format that the Sparc port supports currently
+The 128-bit long double format that the SPARC port supports currently
 works by using the architecturally defined quad-word floating point
 instructions.  Since there is no hardware that supports these
 instructions they must be emulated by the operating system.  Long