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author | Richard Henderson <rth@redhat.com> | 2004-12-22 23:58:41 -0800 |
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committer | Richard Henderson <rth@gcc.gnu.org> | 2004-12-22 23:58:41 -0800 |
commit | 1e0598e25c07970f830bb52f2ae75c7007dea4b4 (patch) | |
tree | 82224c10b6b040c1b09d8cc1ee0b14eb54d26e72 /gcc/doc/md.texi | |
parent | 1c47af84a30650b28b6d1957f1689e2107396a2e (diff) | |
download | gcc-1e0598e25c07970f830bb52f2ae75c7007dea4b4.zip gcc-1e0598e25c07970f830bb52f2ae75c7007dea4b4.tar.gz gcc-1e0598e25c07970f830bb52f2ae75c7007dea4b4.tar.bz2 |
optabs.h (OTI_movmisalign, [...]): New.
* optabs.h (OTI_movmisalign, movmisalign_optab): New.
* optabs.c (init_optabs): Create it.
* genopinit.c (optabs): Initialize it.
* expr.c (expand_expr_real_1) <MISALIGNED_INDIRECT_REF>: Use it.
* tree-vectorizer.c (vect_supportable_dr_alignment): Likewise.
* target-def.h (TARGET_VECTORIZE_MISALIGNED_MEM_OK): Remove.
* target.h (vectorize.misaligned_mem_ok): Remove.
* targhooks.c (default_vect_misaligned_mem_ok): Remove.
* doc/md.texi (movmisalign): New.
* doc/tm.texi (TARGET_VECTORIZE_MISALIGNED_MEM_OK): Remove.
From-SVN: r92537
Diffstat (limited to 'gcc/doc/md.texi')
-rw-r--r-- | gcc/doc/md.texi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 36c73a1..2c41bc4 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2758,6 +2758,17 @@ with mode @var{m} of a register whose natural mode is wider, the @samp{movstrict@var{m}} instruction is guaranteed not to alter any of the register except the part which belongs to mode @var{m}. +@cindex @code{movmisalign@var{m}} instruction pattern +@item @samp{movmisalign@var{m}} +This variant of a move pattern is designed to load or store a value +from a memory address that is not naturally aligned for its mode. +For a store, the memory will be in operand 0; for a load, the memory +will be in operand 1. The other operand is guaranteed not to be a +memory, so that it's easy to tell whether this is a load or store. + +This pattern is used by the autovectorizer, and when expanding a +@code{MISALIGNED_INDIRECT_REF} expression. + @cindex @code{load_multiple} instruction pattern @item @samp{load_multiple} Load several consecutive memory locations into consecutive registers. |