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| author | David S. Miller <davem@davemloft.net> | 2011-10-02 02:21:20 +0000 |
|---|---|---|
| committer | David S. Miller <davem@gcc.gnu.org> | 2011-10-01 19:21:20 -0700 |
| commit | 96d7b15ff3ded45c424b1a240a7db64d3ae975e3 (patch) | |
| tree | 678e9f7f8529fb4e91e2480e8c8e5023253ce0e2 /gcc/doc/invoke.texi | |
| parent | 6a5edb85c2cf7ef821807e16c0ba388c00d22f5e (diff) | |
| download | gcc-96d7b15ff3ded45c424b1a240a7db64d3ae975e3.zip gcc-96d7b15ff3ded45c424b1a240a7db64d3ae975e3.tar.gz gcc-96d7b15ff3ded45c424b1a240a7db64d3ae975e3.tar.bz2 | |
Start adding support for VIS 3.0 instructions.
gcc/
* config/sparc/sparc.opt (VIS3): New option.
* doc/invoke.texi: Document it.
* config/sparc/sparc.h: Force TARGET_VIS3 to zero if assembler is
not capable of such instructions.
* config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__
to 0x300 when TARGET_VIS3.
* config/sparc/sparc-modes.def: Create 16-byte vector modes.
* config/sparc/sparc.md (UNSPEC_CMASK8, UNSPEC_CMASK16, UNSPEC_CMASK32,
UNSPEC_FCHKSM16, UNSPEC_PDISTN, UNSPC_FUCMP): New unspecs.
(V64N8, VASS): New mode iterators.
(vis3_shift, vis3_addsub_ss): New code iterators.
(vbits, vconstr): New mode attributes.
(vis3_shift_insn, vis3_addsub_ss_insn): New code attributes.
(cmask8<P:mode>_vis, cmask16<P:mode>_vis, cmask32<P:mode>_vis,
fchksm16_vis, <vis3_shift_insn><vbits>_vis, pdistn<mode>_vis,
fmean16_vis, fpadd64_vis, fpsub64_vis, <vis3_addsub_ss_insn><vbits>_vis,
fucmp<code>8<P:mode>_vis): New VIS 3.0 instruction patterns.
* config/sparc/sparc.c (sparc_option_override): Set MASK_VIS3 by
default when targetting capable cpus. TARGET_VIS3 implies
TARGET_VIS2 and TARGET_VIS, and clear them when TARGET_FPU is
disabled.
(sparc_vis_init_builtins): Emit new VIS 3.0 builtins.
(sparc_fold_builtin): Do not eliminate cmask{8,16,32} when result
is ignored.
* config/sparc/visintrin.h (__vis_cmask8, __vis_cmask16,
__vis_cmask32, __vis_fchksm16, __vis_fsll16, __vis_fslas16,
__vis_fsrl16, __vis_fsra16, __vis_fsll32, __vis_fslas32,
__vis_fsrl32, __vis_fsra32, __vis_pdistn, __vis_fmean16,
__vis_fpadd64, __vis_fpsub64, __vis_fpadds16, __vis_fpadds16s,
__vis_fpsubs16, __vis_fpsubs16s, __vis_fpadds32, __vis_fpadds32s,
__vis_fpsubs32, __vis_fpsubs32s, __vis_fucmple8, __vis_fucmpne8,
__vis_fucmpgt8, __vis_fucmpeq8): New VIS 3.0 interfaces.
* doc/extend.texi: Document new VIS 3.0 builtins.
gcc/testsuite/
* gcc.target/sparc/cmask.c: New test.
* gcc.target/sparc/fpadds.c: New test.
* gcc.target/sparc/fshift.c: New test.
* gcc.target/sparc/fucmp.c: New test.
* gcc.target/sparc/vis3misc.c: New test.
From-SVN: r179421
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8e43f82..bdc7453 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -880,7 +880,8 @@ See RS/6000 and PowerPC Options. -mstack-bias -mno-stack-bias @gol -munaligned-doubles -mno-unaligned-doubles @gol -mv8plus -mno-v8plus -mvis -mno-vis @gol --mvis2 -mno-vis2 -mfmaf -mno-fmaf} +-mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol +-mfmaf -mno-fmaf} @emph{SPU Options} @gccoptlist{-mwarn-reloc -merror-reloc @gol @@ -17445,6 +17446,16 @@ default is @option{-mvis2} when targetting a cpu that supports such instructions, such as UltraSPARC-III and later. Setting @option{-mvis2} also sets @option{-mvis}. +@item -mvis3 +@itemx -mno-vis3 +@opindex mvis3 +@opindex mno-vis3 +With @option{-mvis3}, GCC generates code that takes advantage of +version 3.0 of the UltraSPARC Visual Instruction Set extensions. The +default is @option{-mvis3} when targetting a cpu that supports such +instructions, such as niagara-3 and later. Setting @option{-mvis3} +also sets @option{-mvis2} and @option{-mvis}. + @item -mfmaf @itemx -mno-fmaf @opindex mfmaf |