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| author | Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> | 2007-03-28 21:44:56 +0000 |
|---|---|---|
| committer | Dwarakanath Rajagopal <dwarak@gcc.gnu.org> | 2007-03-28 21:44:56 +0000 |
| commit | aafc814c7bbf7c176d50a99a3bbf898bc1c2c5dd (patch) | |
| tree | c97a0ec217e78511e5480effb98205e55728724b /gcc/doc/invoke.texi | |
| parent | 71aea5f2e041c542c817a145644760fc0b2bb3d4 (diff) | |
| download | gcc-aafc814c7bbf7c176d50a99a3bbf898bc1c2c5dd.zip gcc-aafc814c7bbf7c176d50a99a3bbf898bc1c2c5dd.tar.gz gcc-aafc814c7bbf7c176d50a99a3bbf898bc1c2c5dd.tar.bz2 | |
Adding barcelona as a variant of amdfam10 architecture
From-SVN: r123313
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f2451c3..38552b7 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -9765,7 +9765,7 @@ instruction set support. @item k8, opteron, athlon64, athlon-fx AMD K8 core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.) -@item amdfam10 +@item amdfam10, barcelona AMD Family 10 core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSE4A, 3dNOW!, enhanced 3dNOW!, ABM and 64-bit instruction set extensions.) |