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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2018-10-31 12:27:35 +0100 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2018-10-31 12:27:35 +0100 |
| commit | aac1c11ce4edd9c2e6af7e9ee8abcaba98d8741f (patch) | |
| tree | 07e0408043af521dfe832f263dea8d6e7cea5011 /gcc/doc/invoke.texi | |
| parent | 8efa18d693207598020f6d7aabb680397ff3815c (diff) | |
| download | gcc-aac1c11ce4edd9c2e6af7e9ee8abcaba98d8741f.zip gcc-aac1c11ce4edd9c2e6af7e9ee8abcaba98d8741f.tar.gz gcc-aac1c11ce4edd9c2e6af7e9ee8abcaba98d8741f.tar.bz2 | |
[ARC] Add BI/BIH instruction support.
Use BI/BIH instruction to implement casesi pattern. Only ARC V2.
gcc/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_override_options): Remove
TARGET_COMPACT_CASESI.
* config/arc/arc.h (ASM_OUTPUT_ADDR_DIFF_ELT): Update.
(CASE_VECTOR_MODE): Likewise.
(CASE_VECTOR_PC_RELATIVE): Likewise.
(CASE_VECTOR_SHORTEN_MODE): Likewise.
(CASE_VECTOR_SHORTEN_MODE1): Delete.
(ADDR_VEC_ALIGN): Update.
(ASM_OUTPUT_CASE_LABEL): Undefine.
(ASM_OUTPUT_BEFORE_CASE_LABEL): Undefine.
(TARGET_BI_BIH): Define.
(DEFAULT_BRANCH_INDEX): Likewise.
* config/arc/arc.md (casesi): Rework to accept BI/BIH
instructions, remove compact_casesi use case.
(casesi_compact_jump): Remove.
(casesi_dispatch): New pattern.
* config/arc/arc.opt: Add mbranch-index option. Deprecate
compact_casesi option.
* doc/invoke.texi: Document mbranch-index option.
gcc/testsuite
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/jumptable.c: New test.
From-SVN: r265675
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3d83bf5..284594d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -651,7 +651,7 @@ Objective-C and Objective-C++ Dialects}. -mmixed-code -mq-class -mRcq -mRcw -msize-level=@var{level} @gol -mtune=@var{cpu} -mmultcost=@var{num} @gol -munalign-prob-threshold=@var{probability} -mmpy-option=@var{multo} @gol --mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu} -mrf16} +-mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu} -mrf16 -mbranch-index} @emph{ARM Options} @gccoptlist{-mapcs-frame -mno-apcs-frame @gol @@ -15839,6 +15839,11 @@ This option instructs the compiler to generate code for a 16-entry register file. This option defines the @code{__ARC_RF16__} preprocessor macro. +@item -mbranch-index +@opindex mbranch-index +Enable use of @code{bi} or @code{bih} instructions to implement jump +tables. + @end table The following options are passed through to the assembler, and also @@ -16010,7 +16015,7 @@ This is the default for @option{-Os}. @item -mcompact-casesi @opindex mcompact-casesi Enable compact @code{casesi} pattern. This is the default for @option{-Os}, -and only available for ARCv1 cores. +and only available for ARCv1 cores. This option is deprecated. @item -mno-cond-exec @opindex mno-cond-exec |