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| author | Olga Makhotina <olga.makhotina@intel.com> | 2018-06-07 11:07:05 +0000 |
|---|---|---|
| committer | Sebastian Peryt <speryt@gcc.gnu.org> | 2018-06-07 13:07:05 +0200 |
| commit | a548a5a1d6bbaeca98787f11f9ff193be1a8cd44 (patch) | |
| tree | 30d15d00259f4b44421b2a7f07cd118beb502796 /gcc/doc/invoke.texi | |
| parent | cef87b05f2114ffc9aad85610eee0ec434ee5703 (diff) | |
| download | gcc-a548a5a1d6bbaeca98787f11f9ff193be1a8cd44.zip gcc-a548a5a1d6bbaeca98787f11f9ff193be1a8cd44.tar.gz gcc-a548a5a1d6bbaeca98787f11f9ff193be1a8cd44.tar.bz2 | |
config.gcc: Support "tremont".
2018-06-07 Olga Makhotina <olga.makhotina@intel.com>
gcc/
* config.gcc: Support "tremont".
* config/i386/driver-i386.c (host_detect_local_cpu): Detect "tremont".
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
PROCESSOR_TREMONT.
* config/i386/i386.c (m_TREMONT): Define.
(processor_target_table): Add "tremont".
(PTA_TREMONT): Define.
(ix86_lea_outperforms): Add TARGET_TREMONT.
(get_builtin_code_for_version): Handle PROCESSOR_TREMONT.
(fold_builtin_cpu): Add M_INTEL_TREMONT, replace M_INTEL_GOLDMONT
and M_INTEL_GOLDMONT_PLUS.
(fold_builtin_cpu): Add "tremont".
(ix86_add_stmt_cost): Add TARGET_TREMONT.
(ix86_option_override_internal): Add "tremont".
* config/i386/i386.h (processor_costs): Define TARGET_TREMONT.
(processor_type): Add PROCESSOR_TREMONT.
* config/i386/x86-tune.def: Add m_TREMONT.
* doc/invoke.texi: Add tremont as x86 -march=/-mtune= CPU type.
gcc/testsuite/
* gcc.target/i386/funcspec-56.inc: Test arch=tremont.
libgcc/
* config/i386/cpuinfo.h (processor_types): Add INTEL_TREMONT.
From-SVN: r261270
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3d767b6..74cb902 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -26660,6 +26660,11 @@ Intel Goldmont Plus CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX and UMIP instruction set support. +@item tremont +Intel Tremont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, +RDPID, SGX, UMIP, GFNI-SSE, CLWB and ENCLV instruction set support. + @item knl Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, |