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author | Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> | 2023-02-18 13:43:34 +0900 |
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committer | Max Filippov <jcmvbkbc@gmail.com> | 2023-02-23 14:31:48 -0800 |
commit | f83e76c3f998c8708fe2ddca16ae3f317c39c37a (patch) | |
tree | a943f505b0fc3fb12eceabf102c2d247407b238f /gcc/doc/cppopts.texi | |
parent | 33e4559305e6f1adaa1b2b59f645d54fd98e5bbe (diff) | |
download | gcc-f83e76c3f998c8708fe2ddca16ae3f317c39c37a.zip gcc-f83e76c3f998c8708fe2ddca16ae3f317c39c37a.tar.gz gcc-f83e76c3f998c8708fe2ddca16ae3f317c39c37a.tar.bz2 |
xtensa: Eliminate unnecessary general-purpose reg-reg moves
Register-register move instructions that can be easily seen as
unnecessary by the human eye may remain in the compiled result.
For example:
/* example */
double test(double a, double b) {
return __builtin_copysign(a, b);
}
test:
add.n a3, a3, a3
extui a5, a5, 31, 1
ssai 1
;; Be in the same BB
src a7, a5, a3 ;; Replacing the destination doesn't
;; violate any constraints of the
;; operands
;; No CALL insns in this span
;; Both A3 and A7 are irrelevant to
;; insns in this span
mov.n a3, a7 ;; An unnecessary reg-reg move
;; A7 is not used after this
ret.n
The last two instructions above, excluding the return instruction,
could be done like this:
src a3, a5, a3
This symptom often occurs when handling DI/DFmode values with SImode
instructions. This patch solves the above problem using peephole2
pattern.
gcc/ChangeLog:
* config/xtensa/xtensa.md: New peephole2 pattern that eliminates
the occurrence of general-purpose register used only once and for
transferring intermediate value.
gcc/testsuite/ChangeLog:
* gcc.target/xtensa/elim_GP_regmove_0.c: New test.
* gcc.target/xtensa/elim_GP_regmove_1.c: New test.
Diffstat (limited to 'gcc/doc/cppopts.texi')
0 files changed, 0 insertions, 0 deletions