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| author | Jin Ma <jinma@linux.alibaba.com> | 2024-08-17 10:18:03 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-08-17 10:18:03 -0600 |
| commit | 6d734ba485547329599f12bea63842a4fba8d72c (patch) | |
| tree | 178db0e0287c5085cd9518e0c57fdf747babb0b2 /gcc/digraph.h | |
| parent | 7aed8dedeb9613925930447bf2457c3fd9972d91 (diff) | |
| download | gcc-6d734ba485547329599f12bea63842a4fba8d72c.zip gcc-6d734ba485547329599f12bea63842a4fba8d72c.tar.gz gcc-6d734ba485547329599f12bea63842a4fba8d72c.tar.bz2 | |
RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics
When rs1 is the immediate 0, the following ICE occurs:
error: unrecognizable insn:
(insn 8 5 12 2 (set (reg:RVVM1DI 134 [ <retval> ])
(if_then_else:RVVM1DI (unspec:RVVMF64BI [
(const_vector:RVVMF64BI repeat [
(const_int 1 [0x1])
])
(reg/v:DI 137 [ vl ])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(plus:RVVM1DI (mult:RVVM1DI (vec_duplicate:RVVM1DI (const_int 0 [0]))
(reg/v:RVVM1DI 136 [ vs2 ]))
(reg/v:RVVM1DI 135 [ vd ]))
(reg/v:RVVM1DI 135 [ vd ])))
gcc/ChangeLog:
* config/riscv/vector.md: Allow scalar operand to be 0.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/bug-7.c: New test.
* gcc.target/riscv/rvv/base/bug-8.c: New test.
Diffstat (limited to 'gcc/digraph.h')
0 files changed, 0 insertions, 0 deletions