RISC-V: Add testcases for form 2 of signed scalar SAT_ADD

This patch would like to add testcases of the signed scalar SAT_ADD
for form 2.  Aka:

Form 2:
  #define DEF_SAT_S_ADD_FMT_2(T, UT, MIN, MAX) \
  T __attribute__((noinline))                  \
  sat_s_add_##T##_fmt_2 (T x, T y)             \
  {                                            \
    T sum = (UT)x + (UT)y;                     \
    if ((x ^ y) < 0 || (sum ^ x) >= 0)         \
      return sum;                              \
    return x < 0 ? MIN : MAX;                  \
  }

DEF_SAT_S_ADD_FMT_2 (int64_t, uint64_t, INT64_MIN, INT64_MAX)

The below test are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat_s_add-5.c: New test.
	* gcc.target/riscv/sat_s_add-6.c: New test.
	* gcc.target/riscv/sat_s_add-7.c: New test.
	* gcc.target/riscv/sat_s_add-8.c: New test.
	* gcc.target/riscv/sat_s_add-run-5.c: New test.
	* gcc.target/riscv/sat_s_add-run-6.c: New test.
	* gcc.target/riscv/sat_s_add-run-7.c: New test.
	* gcc.target/riscv/sat_s_add-run-8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions